Example 2: Four-Byte Clock; Figure 3-2: Four-Byte Clock - Xilinx RocketIO User Manual

Clocking

Example 2: Four-Byte Clock

If a 4-byte or 1-byte data path is chosen, the ratio between USRCLK and USRCLK2
changes. The time it take for the SERDES to serialize the parallel data requires the change
in ratios.
The DCM example
the REFCLK is 156 MHz and the USRCLK2_M only runs at 78 MHz including the clocking
for any interface logic. Both USRCLK and USRCLK2 are aligned on the falling edge, since
USRCLK_M is 180° out of phase when using local inverters with the transceiver.
Clocks for 4-Byte Data Path
VHDL Template
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide
.O ( REFCLKINBUF ));
endmodule
(Figure 3-2) is detailed for a 4-byte data path. If 3.125 Gb/s is required,
NOTE: These local MGT cloock input inverters, shown and noted in
in the FOUR_BYTE_CLK templates.
REFCLK
TXUSRCLK REFCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2

Figure 3-2: Four-Byte Clock

-- Module: FOUR_BYTE_CLK
-- Description: VHDL submodule
-- DCM for 4-byte GT
--
-- Device: Virtex-II Pro Family
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
entity FOUR_BYTE_CLK is
port (
REFCLKIN : in std_logic;
RST : in std_logic;
USRCLK_M : out std_logic;
USRCLK2_M : out std_logic;
REFCLK : out std_logic;
LOCK : out std_logic
);
end FOUR_BYTE_CLK;
--
architecture FOUR_BYTE_CLK_arch of FOUR_BYTE_CLK is
--
-- Components Declarations:
component BUFG
www.xilinx.com
1-800-255-7778
MGT + DCM for 4-Byte Data Path
CLKDV_DIVIDE = 2
IBUFG
DCM
CLKIN CLKDV
CLKFB
RST
CLK0
Figure 3-2, are not included
GT_std_4
0
REFCLKSEL
BUFG
REFCLK
TXUSRCLK2
RXUSRCLK2
TXUSRCLK
RXUSRCLK
MGT clock input inverters
BUFG
(acceptable skew)
UG024_03_020802
R
43