Clock And Data Recovery; Receiver Lock Control; Table 4-7: Cdr Parameters; Table 4-8: Pmarxlocksel[1:0] Definition - Xilinx RocketIO X User Manual

R

Clock and Data Recovery

The serial transceiver input is locked to the input data stream through Clock and Data Recovery
(CDR), a built-in feature of the RocketIO X transceiver. CDR keys off of the rising and falling
edges of incoming data and derives a clock that is representative of the incoming data rate.
The derived clock, RXRECCLK, is generated and locked to as long as it remains within the
specified component range. This clock is presented to the FPGA fabric at 1/16th to 1/40th
the incoming data rate depending on mode. This range is shown in

Table 4-7: CDR Parameters

Parameter
Data Rate Range Serial input differential
(RXP/RXN)
Frequency Offset
T REFCLK duty cycle
DCREF
T /T REFCLK rise and fall time
RCLK FCLK
(see the Virtex-II Pro X
Data Sheet, Module 3)
T REFCLK total jitter
GJTT
T Data run length
UNLOCK
A sufficient number of transitions must be present in the data stream for CDR to work
properly. The CDR circuit is guaranteed to work with 8B/10B and 64B/66B encoding.
Further, CDR requires approximately 5,000 transitions upon power-up to guarantee
locking to the incoming data rate. Once lock is achieved, up to 75 missing transitions can be
tolerated before lock to the incoming data stream is lost.
Another feature of CDR is its ability to accept an external precision clock, REFCLK, which either
acts to clock incoming data or to assist in synchronizing the derived RXRECCLK. REFCLK acts
either to clock incoming data or to assist in synchronizing the derived RXRECCLK.
For further clarity, the TXUSRCLK is used to clock data from the FPGA fabric to the TX
FIFO. The FIFO depth accounts for the slight phase difference between these two clocks. If
the clocks are locked in frequency, then the FIFO acts much like a pass-through buffer.

Receiver Lock Control

During normal operation, the receiver PLL automatically locks to incoming data (when
present) or to the local reference clock (when data is not present). This is the default
configuration for all primitives. This function can be overridden via the
PMARXLOCKSEL[1:0] port, as defined in

Table 4-8: PMARXLOCKSEL[1:0] Definition

When receive PLL lock is forced to the local reference, phase information from the
incoming data stream is ignored. Data continues to be sampled, but synchronous to the
local reference rather than relative to edges in the data stream.
104
Min
2.488
-100
45
PMARXLOCKSEL[1:0]
00
01
10
11
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1-800-255-7778
Chapter 4: Analog Design Considerations
Typ Max Units
10.3125 Gb/s
+100 ppm
50 55 %
TBD ps
TBD ps
72 non
transitions
Table 4-8.
Description
Automatic (Default)
Lock to local reference
Lock to receive data
Reserved (do not use)
RocketIO™ X Transceiver User Guide
Table 4-7.
Conditions
Between 20% and 80%
voltage levels
Peak-to-peak
Requirement when
bypassing 8B/10B
UG035 (v1.5) November 22, 2004