List Of Available Ports - Xilinx RocketIO User Manual

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List of Available Ports

The RocketIO transceiver primitives contain 50 ports, with the exception of the 46-port
GT_ETHERNET and GT_FIBRE_CHAN primitives. The differential serial data ports (RXN, RXP,
TXN, and TXP) are connected directly to external pads; the remaining 46 ports are all accessible
from the FPGA logic (42 ports for GT_ETHERNET and GT_FIBRE_CHAN).
Table 1-5
Table 1-5: GT_CUSTOM
GT_INFINIBAND, and GT_XAUI Primitive Ports
Port
BREFCLK
BREFCLK2
(2)
CHBONDDONE
(2)
CHBONDI
(2)
CHBONDO
CONFIGENABLE
CONFIGIN
CONFIGOUT
(2)
ENCHANSYNC
ENMCOMMAALIGN
ENPCOMMAALIGN
LOOPBACK
POWERDOWN
REFCLK
REFCLK2
24
contains the port descriptions of all primitives.
(1)
, GT_AURORA, GT_FIBRE_CHAN
Port
I/O
Size
I 1 This high-quality reference clock uses dedicated routing to improve jitter for
serial speeds of 2.5 Gb/s or greater. See
I 1 Alternative to BREFCLK. Can be selected by REFCLKSEL.
O 1 Indicates a receiver has successfully completed channel bonding when asserted
High.
I 4 The channel bonding control that is used only by "slaves" which is driven by a
transceiver's CHBONDO port.
O 4 Channel bonding control that passes channel bonding and clock correction
control to other transceivers.
I 1 Reconfiguration enable input (unused)
I 1 Data input for reconfiguring transceiver (unused)
O 1 Data output for configuration readback (unused)
I 1 Comes from the core to the transceiver and enables the transceiver to perform
channel bonding
I 1 Selects realignment of incoming serial bitstream on minus-comma. High
realigns serial bitstream byte boundary when minus-comma is detected.
I 1 Selects realignment of incoming serial bitstream on plus-comma. High realigns
serial bitstream byte boundary when plus-comma is detected.
I 2 Selects the two loopback test modes. Bit 1 is for serial loopback and bit 0 is for
internal parallel loopback.
I 1 Shuts down both the receiver and transmitter sides of the transceiver when
asserted High. This decreases the power consumption while the transceiver is
shut down. This input is asynchronous.
I 1 High-quality reference clock driving transmission (reading TX FIFO, and
multiplied for parallel/serial conversion) and clock recovery. REFCLK
frequency is accurate to ±100 ppm. This clock originates off the device, is
routed through fabric interconnect, and is selected by REFCLKSEL.
I 1 An alternative to REFCLK. Can be selected by REFCLKSEL.
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Chapter 1: RocketIO Transceiver Overview
(2) (2)
, GT_ETHERNET ,
Definition
Table 2-2, page 40
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
for usage cases.