Example 3: One-Byte Clock - Xilinx RocketIO User Manual

Clocking

Example 3: One-Byte Clock

This is the 1-byte data path width clocking scheme example. USRCLK2_M is twice as fast as
USRCLK_M. It is also phase-shifted 180° for falling edge alignment.
Clocks for 1-Byte Data Path
VHDL Template
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
.O ( REFCLKINBUF )
);
endmodule
REFCLK
TXUSRCLK
REFCLK_P
RXUSRCLK
REFCLK_N
TXUSRCLK2
RXUSRCLK2
Figure 2-5: One-Byte Clock
-- Module: ONE_BYTE_CLK
-- Description: VHDL submodule
-- DCM for 1-byte GT
--
-- Device: Virtex-II Pro Family
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
entity ONE_BYTE_CLK is
port (
REFCLKIN : in std_logic;
RST : in std_logic;
USRCLK_M : out std_logic;
USRCLK2_M : out std_logic;
REFCLK : out std_logic;
LOCK : out std_logic
);
end ONE_BYTE_CLK;
--
architecture ONE_BYTE_CLK_arch of ONE_BYTE_CLK is
--
-- Components Declarations:
component BUFG
port (
I : in std_logic;
O : out std_logic
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MGT + DCM for 1-Byte Data Path
IBUFGDS
DCM
CLKIN CLK2X180
CLKFB
RST
CLK0
GT_std_1
0
REFCLKSEL
BUFG
REFCLK
TXUSRCLK2
RXUSRCLK2
TXUSRCLK
RXUSRCLK
BUFG
UG024_04_112202
51
R