Clock Ratio; Digital Clock Manager (Dcm) Examples - Xilinx RocketIO User Manual

Clocking

Clock Ratio

USRCLK2 clocks the data buffers. The ability to send/receive parallel data to/from the transceiver
at three different widths requires the user to change the frequency of USRCLK2. This creates a
frequency ratio between USRCLK and USRCLK2. The falling edges of the clocks must align.
Table 2-4
Table 2-4: Data Width Clock Ratios

Digital Clock Manager (DCM) Examples

With at least three different clocking schemes possible on the transceiver, a DCM is the best way to
create these schemes.
Table 2-5
reference clock for the DCM. The other clocks are generated by the DCM. The DCM establishes a
desired phase relationship between TXUSRCLK, TXUSRCLK2, etc. in the FPGA core and
REFCLK at the pad.
NOTE: The reference clock may be any of the four MGT clocks, including the BREFCLKs.
Table 2-5: DCM Outputs for Different DATA_WIDTHs
TX_DATA_WIDTH
SERDES_10B
RX_DATA_WIDTH
FALSE
FALSE
FALSE
TRUE
TRUE
TRUE
Notes:
1. Since CLK0 is needed for feedback, it can be used instead of CLK180 to clock USRCLK or USRCLK2 of the transceiver with the use of the
transceiver's local inverter, saving a global buffer (BUFG).
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
shows the ratios for each of the three data widths.
Data Width
1 byte
2 byte
4 byte
Notes:
1. Each edge of the slower clock must align with the falling edge of the faster clock.
shows typical DCM connections for several transceiver clocks. REFCLK is the input
REFCLK
1
2
4
1
2
4
Frequency Ratio of USRCLK\USRCLK2
TXUSRCLK
RXUSRCLK
CLKIN CLK0
CLKIN CLK0
CLKIN CLK180
CLKIN CLKDV (divide by 2)
CLKIN CLKDV (divide by 2)
CLKIN CLKFX180 (divide by 2)
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(1)
1:2
1:1
(1)
2:1
TXUSRCLK2
RXUSRCLK2
CLK2X180
CLK0
(1)
CLKDV (divide by 2)
CLK180
CLKDV (divide by 2)
CLKDV (divide by 4)
R
(1)
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