Clock And Data Recovery - Xilinx RocketIO User Manual

R
Deterministic Jitter (DJ) is data pattern dependant jitter, attributed to a unique source (e.g., Inter
Symbol Interference (ISI) due to loss effects of the media). DJ is linearly additive.
Random Jitter (RJ) is due to stochastic sources, such as substrate, power supply, etc. RJ is additive
as the sum of squares, and follows a bell curve.

Clock and Data Recovery

The serial transceiver input is locked to the input data stream through Clock and Data Recovery
(CDR), a built-in feature of the RocketIO transceiver. CDR keys off the rising and falling edges of
incoming data and derives a clock that is representative of the incoming data rate.
The derived clock, RXRECCLK, is presented to the FPGA fabric at 1/20th the incoming data rate
(whether full-rate or half-rate). This clock is generated and remains locked as long as it remains
within the specified component range. This range is shown in
A sufficient number of transitions must be present in the data stream for CDR to work properly. The
CDR circuit is guaranteed to work with 8B/10B encoding. Further, CDR requires approximately
5,000 transitions upon power-up to guarantee locking to the incoming data rate. Once lock is
achieved, up to 75 missing transitions can be tolerated before lock to the incoming data stream is
lost.
Table 3-4: CDR Parameters
An additional feature of CDR is its ability to accept an external precision clock, REFCLK, which
either acts to clock incoming data or to assist in synchronizing the derived RXRECCLK.
106
Parameter
Frequency Range Serial input, diff.
(RXP/RXN)
TDCREF REFCLK
TRCLK/TFCLK REFCLK
time (see Virtex-II Pro
Data Sheet, Module 3)
TGJTT REFCLK
(2)
jitter,
(3)
TLOCK Clock recovery
frequency acquisition
time
TUNLOCK
PLL length
Notes:
1. BREFCLK for speeds of 2.5 Gb/s or greater.
2. Jitter measured at BGA ball.
3. T depends on serial speed and length/type of sequence used.
LOCK
Chapter 3: Analog Design Considerations
Min Typ
300
(1)
duty cycle 45 50
(1)
rise and fall 400
(1)
total
peak-to-peak
10
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Table 3-4.
Max Units Conditions
1,562.5 MHz
55 %
1000 ps Between 20% and
80% voltage levels
40 ps 3.125 Gb/s
50 ps 2.5 Gb/s
120 ps 1.06 Gb/s
µs From system reset.
Much less time is
needed to lock if
loss of sync occurs
(T
phase
described in
Module 3.
cycles
75 non- Requirement when
transitions bypassing 8B/10B
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
), which is