Ucf Example; Implementing Clock Schemes; Figure 5-1: 2Vp2 Implementation; Figure 5-2: 2Vp50 Implementation - Xilinx RocketIO User Manual

R
SLAVE_1_HOP SLAVE_1_HOP
CHBONDI CHBONDO CHBONDI CHBONDO
CHBONDO CHBONDI CHBONDO CHBONDI
SLAVE_2_HOPS SLAVE_2_HOPS

UCF Example

4.2 ns is estimated as the channel bonding delay. This is based upon an RXUSRCLK of
156.25 MHz (6.4 ns period), less 0.2 ns for estimated clock skew, less 2.0 ns for estimated
clock-to-out/setup-time adjustment:
This design used four RocketIO multi-gigabit transceivers, consisting of one master, two
Slave_1_hop, and one Slave_2_hops. The net chbond_m_s01[3:0] connects the master
and two Slave_1_hop. The net chbond_s1_s2[3:0] connects one Slave_1_hop and one
Slave_2_hops.

Implementing Clock Schemes

Sometimes certain FPGA resources are needed for specific logic. With RocketIO clocking
schemes, the user has several resource choices. If the transceivers implemented are only at
the top or bottom of the device, the REFCLK of the transceivers is not required to run
through a clock tree resource. This saves this resource for other user logic. However, it does
require additional I/O pins to be used (one for the DCM and one for the transceiver).
Figure 3-3, page
resource. If transceivers from both the top and bottom of the device are used or device I/Os
are at a premium, the clock tree resource is used allowing one less I/O pin used.
98
MASTER
CHBONDI CHBONDO
CHBONDI CHBONDO
SLAVE_1_HOP

Figure 5-1: 2VP2 Implementation

SLAVE_1_HOP MASTER
CHBONDI CHBONDO CHBONDI CHBONDO
CHBONDO CHBONDI CHBONDO CHBONDI
SLAVE_2_HOPS SLAVE_1_HOP

Figure 5-2: 2VP50 Implementation

NET "chbond_*" MAXDELAY = 4.2 ns ;
6.4 ns – 0.2 ns – 2.0 ns = 4.2 ns
NET "chbond_*" MAXDELAY = 4.2 ns ;
46, shows this scenario, which is similar to
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Chapter 5: Simulation and Implementation
SLAVE_1_HOP
CHBONDI
CHBONDI
SLAVE_2_HOPS
SLAVE_1_HOP SLAVE_1_HOP
CHBONDI CHBONDO CHBONDI CHBONDO
CHBONDO CHBONDI CHBONDO CHBONDI
SLAVE_2_HOPS SLAVE_2_HOPS
constrains all these connections.
RocketIO™ Transceiver User Guide
CHBONDO
Top of device
Bottom of device
CHBONDO
UG024_08_020802
SLAVE_1_HOP SLAVE_1_HOP
CHBONDI CHBONDO CHBONDI CHBONDO
Top of device
Bottom of device
CHBONDO CHBONDI CHBONDO CHBONDI
SLAVE_2_HOPS SLAVE_2_HOPS
UG024_08_020802
Figure 3-1 minus the clock-tree
UG024 (v1.5) October 16, 2002