Figure 2-1: Rocketio Transceiver Block Diagram; Table 2-3: Serial Baud Rates And The Serdes_10B Attribute - Xilinx RocketIO User Manual

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Table 2-3: Serial Baud Rates and the SERDES_10B Attribute

PACKAGE
PINS
AVCCAUXRX
2.5V RX
VTRX
Termination Supply RX
RXP
RXN
TXP
TXN
GNDA
TX/RX GND
AVCCAUXTX
2.5V TX
VTTX
Termination Supply TX
16
SERDES_10B
False
True
MULTI-GIGABIT TRANSCEIVER CORE
Power Down
Comma
Detect
Deserializer
Realign
Clock
Manager
Serializer Output
Polarity

Figure 2-1: RocketIO Transceiver Block Diagram

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Chapter 2: RocketIO Transceiver Overview
Serial Baud Rate
800 Mb/s – 3.125 Gb/s
622 Mb/s – 1.0 Gb/s
CRC
Check
RX
Elastic
Buffer
8B/10B
Decoder
Channel Bonding
and
Clock Correction
8B/10B
TX
CRC
FIFO Encoder
RocketIO™ Transceiver User Guide
FPGA FABRIC
POWERDOWN
RXRECCLK
RXPOLARITY
RXREALIGN
RXCOMMADET
ENPCOMMAALIGN
ENMCOMMAALIGN
RXCHECKINGCRC
RXCRCERR
RXDATA[15:0]
RXDATA[31:16]
RXNOTINTABLE[3:0]
RXDISPERR[3:0]
RXCHARISK[3:0]
RXCHARISCOMMA[3:0]
RXRUNDISP[3:0]
RXBUFSTATUS[1:0]
ENCHANSYNC
CHBONDDONE
CHBONDI[3:0]
CHBONDO[3:0]
RXLOSSOFSYNC
RXCLKCORCNT
TXBUFERR
TXFORCECRCERR
TXDATA[15:0]
TXDATA[31:16]
TXBYPASS8B10B[3:0]
TXCHARISK[3:0]
TXCHARDISPMODE[3:0]
TXCHARDISPVAL[3:0]
TXKERR[3:0]
TXRUNDISP[3:0]
TXPOLARITY
TXINHIBIT
LOOPBACK[1:0]
TXRESET
RXRESET
REFCLK
REFCLK2
REFCLKSEL
BREFCLK
BREFCLK2
RXUSRCLK
RXUSRCLK2
TXUSRCLK
TXUSRCLK2
DS083-2_04_090402
UG024 (v1.5) October 16, 2002