Bit Alignment Design; Verilog - Xilinx RocketIO User Manual

Product Not Recommended for New Designs
Other Important Design Notes

32-bit Alignment Design

The following example code illustrates one way to create the logic to properly align 32-bit
wide data with a comma in bits [31:24] For brevity, most status bits are not included in this
example design; however, these should be shifted in the same manner as RXDATA and
RXCHARISK.
Note that when using a 40-bit data path (8B/10B bypassed), a similar realignment scheme
may be used, but it cannot rely on RXCHARISCOMMA for comma detection.

Verilog

RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
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// Virtex-II Pro RocketIO comma alignment module
//
// This module reads RXDATA[31:0] from a RocketIO transceiver
// and copies it to
// its output, realigning it if necessary so that commas
// are aligned to the MSB position
// [31:24]. The module assumes ALIGN_COMMA_MSB is TRUE,
// so that the comma
// is already aligned to [31:24] or [15:8].
//
// Outputs
//
// aligned_data[31:0] -- Properly aligned 32-bit ALIGNED_DATA
// sync -- Indicator that aligned_data is properly aligned
// aligned_rxisk[3:0] - properly aligned 4 bit RXCHARISK
// Inputs - These are all RocketIO inputs or outputs
// as indicated:
//
// usrclk2 -- RXUSRCLK2
// rxreset -- RXRESET
// rxisk[3:0] RXCHARISK[3:0]
// rxdata[31:0] RXDATA[31:0] -- (commas aligned to
//
// rxrealign -- RXREALIGN
// rxcommadet -- RXCOMMADET
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[31:24] or [15:8])
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