High-Speed Serial Trace Design; Routing Serial Traces; Figure 4-8: Example Power Filtering Pcb Layout For Four Mgts, Top Layer; Figure 4-9: Example Power Filtering Pcb Layout For Four Mgts, Bottom Layer - Xilinx RocketIO User Manual

PCB Design Requirements
All AVCCAUXTX and AVCCAUXRX pins in a Virtex-II Pro device must be connected to
2.5 V, regardless of whether or not they are used. See
and

High-Speed Serial Trace Design

Routing Serial Traces

All RocketIO transceiver I/Os are placed on the periphery of the BGA package to facilitate
routing and inspection (since JTAG is not available on serial I/O pins). Two output/input
impedance options are available in the RocketIO transceivers: 50Ω and 75Ω. Controlled
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide

Figure 4-8: Example Power Filtering PCB Layout for Four MGTs, Top Layer

Figure 4-9: Example Power Filtering PCB Layout for Four MGTs, Bottom Layer

The POWERDOWN Port, page
www.xilinx.com
1-800-255-7778
Powering the RocketIO Transceivers
95, for details.
R
UG024_27_022202
UG024_28_022202
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