32-Bit Alignment Design; Verilog; Figure 3-20: Realignment Of Rxdata - Xilinx RocketIO User Manual

R
When RXDATA is 32-bit misaligned, the word requiring alignment is split between
consecutive RXDATA words in the data stream, as shown in
This conditional shift/delay operation on RXDATA also must be performed on the status
outputs RXNOTINTABLE, RXDISPERR, RXCHARISK, RXCHARISCOMMA, and
RXRUNDISP in order to keep them properly synchronized with RXDATA.
It is not possible to adjust RXCLKCORCNT appropriately for shifted/delayed RXDATA,
because RXCLKCORCNT is summary data, and the summary for the shifted case cannot
be recalculated.

32-bit Alignment Design

The following example code illustrates one way to create the logic to properly align 32-bit
wide data with a comma in bits [31:24] For brevity, most status bits are not included in this
example design; however, these should be shifted in the same manner as RXDATA and
RXCHARISK.
Note that when using a 40-bit data path (8B/10B bypassed), a similar realignment scheme
may be used, but it cannot rely on RXCHARISCOMMA for comma detection.

Verilog

76
TXDATA
BC95B5B5
RXDATA pppp BC95
RXDATA_REG[15:0]
ALIGNED_DATA
pppppppp

Figure 3-20: Realignment of RXDATA

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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
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// Virtex-II Pro RocketIO comma alignment module
//
www.xilinx.com
1-800-255-7778
Chapter 3: Digital Design Considerations
FDB53737 45674893
B5B5FDB5 37374567
pppp BC95 FDB5
pppppppp
BC95B5B5
BY PROVIDING THIS DESIGN, CODE,
XILINX EXPRESSLY DISCLAIMS ANY
Figure 3-20.
nnnnnnnn nnnnnnnn
4893 nnnn nnnnnnnn
4567 nnnn
FDB53737 45674893
ug024_34_091602
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide