Clock Synthesizer; Table 2-4: Supported Rocketio Transceiver Primitives; Table 3-1: Gt_Custom; Gt_Ethernet - Xilinx RocketIO User Manual

Clock Synthesizer

Table 2-4
attributes set to default values for the communications protocols listed in
widths of one, two, and four bytes are selectable for each protocol.

Table 2-4: Supported RocketIO Transceiver Primitives

There are two ways to modify the RocketIO transceiver:
•
•
The RocketIO transceiver consists of the Physical Media Attachment (PMA) and Physical
Coding Sublayer (PCS). The PMA contains the serializer/deserializer (SERDES), TX and
RX buffers, clock generator, and clock recovery circuitry. The PCS contains the 8B/10B
encoder/decoder and the elastic buffer supporting channel bonding and clock correction.
The PCS also handles Cyclic Redundancy Check (CRC). Refer again to
the RocketIO transceiver top-level block diagram and FPGA interface signals.
Clock Synthesizer
Synchronous serial data reception is facilitated by a clock/data recovery circuit. This
circuit uses a fully monolithic Phase-Locked Loop (PLL), which does not require any
external components. The clock/data recovery circuit extracts both phase and frequency
from the incoming data stream. The recovered clock is presented on output RXRECCLK at
1/20 of the serial received data rate.
The gigabit transceiver multiplies the reference frequency provided on the reference clock
input (REFCLK) by 20.
No fixed phase relationship is assumed between REFCLK, RXRECCLK, and/or any other
clock that is not tied to either of these clocks. When the 4-byte or 1-byte receiver data path
is used, RXUSRCLK and RXUSRCLK2 have different frequencies (1:2), and each edge of
the slower clock is aligned to a falling edge of the faster clock. The same relationships
apply to TXUSRCLK and TXUSRCLK2. See the section entitled
details.
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide
lists the 16 gigabit transceiver primitives provided. These primitives carry
Primitives
GT_CUSTOM Fully customizable
by user
GT_FIBRE_CHAN_1 Fibre Channel,
1-byte data path
GT_FIBRE_CHAN_2 Fibre Channel,
2-byte data path
GT_FIBRE_CHAN_4 Fibre Channel,
4-byte data path

GT_ETHERNET_1

Gigabit Ethernet,
1-byte data path
GT_ETHERNET_2 Gigabit Ethernet,
2-byte data path
GT_ETHERNET_4 Gigabit Ethernet,
4-byte data path
GT_XAUI_1 10-Gb Ethernet,
1-byte data path
Static properties can be set through attributes in the HDL code. Use of attributes are
covered in detail in Primitive Attributes, page
Dynamic changes can be made by the ports of the primitives
www.xilinx.com
1-800-255-7778
Description
GT_XAUI_2
GT_XAUI_4
GT_INFINIBAND_1
GT_INFINIBAND_2
GT_INFINIBAND_4
GT_AURORA_1
GT_AURORA_2
GT_AURORA_4
29.
Table
Primitive Description
10-Gb Ethernet,
2-byte data path
10-Gb Ethernet,
4-byte data path
Infiniband, 1-byte
data path
Infiniband, 2-byte
data path
Infiniband, 4-byte
data path
Xilinx protocol,
1-byte data path
Xilinx protocol,
2-byte data path
Xilinx protocol,
4-byte data path
Figure 2-1, showing
Clocking, page
R
2-2. Data
38, for
17