High-Speed Serial Trace Design; Routing Serial Traces; Figure 4-23: Example Power Filtering Pcb Layout For Four Mgts - Xilinx RocketIO X User Manual

PCB Design Requirements
VTRX. The ferrite beads are mounted at the 16 "L[n]" locations (highlighted by the colored
circles).

Figure 4-23: Example Power Filtering PCB Layout for Four MGTs

All AVCCAUXTX and AVCCAUXRX pins in a Virtex-II Pro X device must be connected to
2.5V/1.5V regardless of whether or not they are used. See
Transceivers," page 121

High-Speed Serial Trace Design

Routing Serial Traces

All RocketIO X transceiver I/Os are placed on the periphery of the BGA package to facilitate
routing and inspection (since JTAG is not available on serial I/O pins). RocketIO X
transceivers have a 50Ω output/input impedance. Controlled impedance traces should be
used to connect the RocketIO X transceiver to other compatible transceivers.
When routing a differential pair, the complementary traces must be matched in length to as
close a tolerance as is feasible. Length mismatches produce common mode noise and
radiation. Severe length mismatches produce jitter and unpredictable timing problems at
the receiver. Matching the differential traces to within 50 mils (1.27 mm) produces a robust
design. Since signals propagate in FR4 PCB traces at approximately 180 ps per inch, a
difference of 50 mils produces a timing skew of roughly 9 ps. Use SI CAD tools to confirm
these assumptions on specific board designs.
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
(In Device With Internal Capacitors), Bottom Layer
and "POWERDOWN Port," page 121
www.xilinx.com
1-800-255-7778
ug)35_ch4_23a_021304
"Powering the RocketIO X
for details.
R
117