Functions Common To All Protocols; Clock Correction; Append/Remove Idle Clock Correction - Xilinx RocketIO X User Manual

Block Level Functions
The state machine works by keeping track of valid and invalid sync headers. Upon reset,
block lock is deasserted, and the state is LOCK_INIT. The next state is RESET_CNT where
all counters are zeroed out. When test_sh is asserted, the next state is TEST_SH, which
checks the validity of the sync header. If it is valid, the next state is VALID_SH, if not, the
state changes to INVALID_SH.
From VALID_SH, if sh_cnt is less than the attribute value sh_cnt_max and test_sh is
High, the next state is TEST_SH. If sh_cnt is equal to sh_cnt_max and
sh_invalid_cnt equals 0, the next state is GOOD_64 and from there block_lock is
asserted. Then the process repeats again and the counters are zeroed.
If at TEST_SH sh_cnt equals sh_cnt_max, but sh_invalid_cnt is greater than zero,
then the next state is RESET_CNT. From INVALID_SH, if sh_invalid_cnt equals
sh_invalid_cnt_max, or if block_lock is not asserted, the next state is SLIP, where
bit_slip is asserted, and then on to RESET_CNT. If sh_cnt equals sh_cnt_max and
sh_invalid_cnt is less than sh_invalid_cnt_max and block_lock is asserted, then
go back to RESET_CNT without changing block_lock or bit_slip.
Finally, if test_sh is High and sh_cnt is less than sh_cnt_max, and
sh_invalid_cnt is less than sh_invalid_cnt_max and block_lock is asserted, go
back to the TEST_SH state. The main thing to note with this state machine is that to
achieve block lock, one must receive sh_cnt_max number of valid sync headers in a
row without getting an invalid sync header. However, once block lock is achieved,
sh_invalid_cnt_max -1 number of invalid sync headers can be received within
sh_cnt_max number of valid sync headers. Thus, once locked, it is harder to break lock.

Functions Common to All Protocols

Clock Correction

Clock correction is needed when the rate that data is fed into the write side of the receive
FIFO is either slower or faster than the rate that data is retrieved from the read side of the
receive FIFO. The rate of write data entering the FIFO is determined by the frequency of
RXRECCLK. The rate of read data retrieved from the read side of the FIFO is determined
by the frequency of RXUSRCLK.
There is one clock correction mode: Append/Remove Idle Clock Correction.

Append/Remove Idle Clock Correction

When the attribute CLK_COR_SEQ_DROP is asserted Low and CLK_CORRECT_USE is
asserted hIgh, the Append/remove Idle Clock Correction mode is enabled.
The Append/remove Idle Clock Correction mode corrects for differing clock rates by
finding idles in the bitstream, and then either appending or removing idles at the point
where the idles were found.
There are a few attributes that need to be set by the user so that the append/remove
function can be used correctly. The attribute CLK_COR_MAX_LAT sets the maximum
latency through the receive FIFO. If the latency through the receive FIFO exceeds this
value, idles are removed so that latency through the receive FIFO is less than
CLK_COR_MAX_LAT.
The attribute CLK_COR_MIN_LAT sets the minimum latency through the receive FIFO. If
the latency through the receive FIFO is less than this value, idles are inserted so that the
latency through the receive FIFO are greater than CLK_COR_MIN_LAT. A correction to
the latency due to a CLK_COR_MAX_LAT violation is never less than
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
www.xilinx.com
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