Clock Correction - Xilinx RocketIO User Manual

Clock Recovery
REFCLK, RXUSRCLK, and the incoming stream (RXRECCLK) must not exceed ±100 ppm of
frequency variation.
It is critical to keep power supply noise low in order to minimize common and differential noise
modes into the clock/data recovery circuitry. See
details.

Clock Correction

Clock RXRECCLK (the recovered clock) reflects the data rate of the incoming data. Clock
RXUSRCLK defines the rate at which the FPGA core consumes the data. Ideally, these rates are
identical. However, since the clocks typically have different sources, one of the clocks is faster than
the other. The receiver buffer accommodates this difference between the clock rates. See
Figure
Nominally, the buffer is always half-full. This is shown in the top buffer, where the shaded area
represents buffered data not yet read. Received data is inserted via the write pointer under control of
RXRECCLK. The FPGA core reads data via the read pointer under control of RXUSRCLK. The
half-full/half-empty condition of the buffer gives a cushion for the differing clock rates. This
operation continues indefinitely, regardless of whether or not "meaningful" data is being received.
When there is no meaningful data to be received, the incoming data consists of IDLE characters or
other padding.
If RXUSRCLK is faster than RXRECCLK, the buffer becomes more empty over time. The clock
correction logic corrects for this by decrementing the read pointer to reread a repeatable byte
sequence. This is shown in the middle buffer,
to the value represented by the dashed pointer. By decrementing the read pointer instead of
incrementing it in the usual fashion, the buffer is partially refilled. The transceiver inserts a single
repeatable byte sequence when necessary to refill a buffer. If the byte sequence length is greater than
one, and if attribute CLK_COR_REPEAT_WAIT is 0, then the transceiver can repeat the same
sequence multiple times until the buffer is refilled to the half-full condition.
Similarly, if RXUSRCLK is slower than RXRECCLK, the buffer fills up over time. The clock
correction logic corrects for this by incrementing the read pointer to skip over a removable byte
sequence that need not appear in the final FPGA core byte stream. This is shown in the bottom
buffer,
pointer. This accelerates the emptying of the buffer, preventing its overflow. The transceiver design
skips a single byte sequence, when necessary, to partially empty a buffer. If attribute
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
2-20.
Read
RXUSRCLK
Read
Removable sequence
Figure 2-20: Clock Correction in Receiver
Figure 2-20, where the solid read pointer increments to the value represented by the dashed
www.xilinx.com
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"PCB Design Requirements," page
RXRECCLK
"Nominal" condition: buffer half-full
Read Write
Buffer less than half -full (emptying)
Repeatable sequence
Buffer more than half-full (filling up)
Figure 2-20, where the solid read pointer decrements
107, for more
Write
Write
DS083-2_15_100901
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