Figure A-1: Rocketio X Transceiver Block Diagram - Xilinx RocketIO X User Manual

PACKAGE
AVCCAUXTX
AVCCAUXRX
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
PINS
MULTI-GIGABIT TRANSCEIVER CORE
2.5V
VTRX
Termination Supply RX
RXP
RXN
Deserializer
Clock
Manager
TXP
Serializer
TXN
GNDA
TX/RX GND
1.5V
VTTX
Termination Supply TX

Figure A-1: RocketIO X Transceiver Block Diagram

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1-800-255-7778
Power Down
64B/66B
Descrambler
RX
Comma
Elastic
Detect
Buffer
8B/10B
Realign
Decoder
Channel Bonding
64B/66B
and
Block Sync
Clock Correction
Gear
64B/66B
Box
Encoder
Scrambler
TX
8B/10B
FIFO
Encoder
Output
Polarity
Attribute
FPGA FABRIC
POWERDOWN
RXRECCLK
RXPOLARITY
RXREALIGN
RXCOMMADET
ENPCOMMAALIGN
ENMCOMMAALIGN
RXDATA[63:0]
RXNOTINTABLE[7:0]
RXDISPERR[7:0]
RXCHARISK[7:0]
RXCHARISCOMMA[7:0]
RXRUNDISP[7:0]
RXBUFSTATUS[1:0]
ENCHANSYNC
CHBONDDONE
CHBONDI[4:0]
CHBONDO[4:0]
RXLOSSOFSYNC[1:0]
RXCLKCORCNT[2:0]
TXBUFERR
TXDATA[63:0]
TXBYPASS8B10B[7:0]
TXCHARISK[7:0]
TXCHARDISPMODE[7:0]
TXCHARDISPVAL[7:0]
TXKERR[7:0]
TXRUNDISP[7:0]
TXPOLARITY
TXINHIBIT
LOOPBACK[1:0]
TXRESET
RXRESET
REFCLK
REFCLK2
REFCLKSEL
Clock /
BREFCLKP
Reset
BREFCLKN
RXUSRCLK
RXUSRCLK2
TXUSRCLK
TXUSRCLK2
PMAINIT
PMAREGADDR[5:0]
PMA
PMAREGDATAIN[7:0]
PMAREGRW
Load
PMAREGSTROBE
PMARXLOCKSEL[1:0]
PMARXLOCK
REFCLKBSEL
RXBLCOKSYNC64B66BUSE
RXCOMMADETUSE
RXDATAWIDTH[1:0]
RXDECC64B66BUSE
RXDEC8B10BUSE
RXDESCRAM64B66BUSE
RXIGNOREBTF
RXINTDATAWIDTH[1:0]
RXSLIDE
TXDATAWIDTH[1:0]
TXENC64B66BUSE
TXENC8B10BUSE
TXGEARBOX64B66BUSE
TXINTDATAWIDTH[1:0]
TXSCRAM64B66BUSE
TXOUTCLK
UG035_01_111303
R
131