Half-Rate Clocking Scheme; Figure 3-5: One-Byte Data Path Clocks, Serdes_10B = True; Figure 3-6: Two-Byte Data Path Clocks, Serdes_10B = True; Figure 3-7: Four-Byte Data Path Clocks, Serdes_10B = True - Xilinx RocketIO User Manual

R

Half-Rate Clocking Scheme

Some applications require serial speeds between 622 Mb/s and 1 Gb/s. The transceiver
attribute SERDES_10B, which sets the REFCLK multiplier to 10 instead of 20, enables the
half-rate speed range when set to TRUE. With this configuration, the clocking scheme also
changes. The figures below illustrate the three clocking scheme waveforms when
SERDES_10B = TRUE.
52
Clocks for 1-Byte Data Path
(SERDES_10B = TRUE)

Figure 3-5: One-Byte Data Path Clocks, SERDES_10B = TRUE

Clocks for 2-Byte Data Path
(SERDES_10B = TRUE)

Figure 3-6: Two-Byte Data Path Clocks, SERDES_10B = TRUE

Clocks for 4-Byte Data Path
(SERDES_10B = TRUE)

Figure 3-7: Four-Byte Data Path Clocks, SERDES_10B = TRUE

www.xilinx.com
1-800-255-7778
Chapter 3: Digital Design Considerations
REFCLK
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
UG024_29_051302
REFCLK
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
UG024_30_051302
REFCLK
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
UG024_31_051302
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide