Crc Generation; Crc Latency - Xilinx RocketIO User Manual

R
Ethernet and Fibre Channel, transmitter CRC can adjust certain trailing bytes to generate the
required running disparity at the end of the packet. This is discussed further in the
and
On the receiver side, the CRC logic verifies the received CRC value, supporting the same standards
as above.

CRC Generation

RocketIO transceivers support a 32-bit invariant CRC (fixed 32-bit polynomial shown below) for
Gigabit Ethernet, Fibre Channel, Infiniband, and user-defined modes.
The CRC recognizes the SOP (Start of Packet), EOP (End of Packet), and other packet features to
identify the beginning and end of data. These SOP and EOP are defined by CRC_FORMAT for
ETHERNET, INFINIBAND, and FIBRE_CHAN, and in these cases the user does not need to set
CRC_START_OF_PKT and CRC_END_OF_PKT. Where CRC_FORMAT is USER_MODE
(user-defined), CRC_START_OF_PKT and CRC_END_OF_PKT are used to define SOP and EOP.
...
SOP
The transmitter computes 4-byte CRC on the packet data between the SOP and EOP (excluding the
CRC placeholder bytes). The transmitter inserts the computed CRC just before the EOP. The
transmitter modifies trailing Idles or EOP if necessary to generate correct running disparity for
Gigabit Ethernet and Fibre Channel. The receiver recomputes CRC and verifies it against the
inserted CRC.
used in certain protocols (Ethernet). The user logic must create a four-byte placeholder for the CRC
by placing it in TXDATA. Otherwise, data is overwritten.

CRC Latency

Enabling CRC increases the transmission latency from TXDATA to TXP and TXN. The enabling of
CRC does not affect the latency from RXP and RXN to RXDATA. The typical and maximum
latencies, expressed in TXUSRCLK/RXUSRCLK cycles, are shown in
diagrams expressing these relationships, please see Module 3 of the
Table 2-20: Effects of CRC on Transceiver Latency
CRC Disabled
84
"ETHERNET" sections under
32 26 23 22
x + x + x + x
Data
Figure 2-23: CRC Packet Format
Figure 2-23 shows the packet format for CRC generation. The empty boxes are only
TXDATA to TXP and TXN
in TXUSRCLK Cycles
Typical Maximum
8 11
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Chapter 2: Digital Design Considerations
"CRC_FORMAT," page
16 12 11 10
+ x + x + x + x
CRC
4 Bytes
(1)
RXP and RXN to RXDATA
in RXUSRCLK Cycles
Typical
25
"FIBRE_CHAN"
85.
8 7 5 4 2
+ x + x + x + x + x
... ...
EOP
Table 2-20. For timing
Virtex-II Pro Data
(3)
Maximum
(2)
42
RocketIO™ Transceiver User Guide
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+ x + 1
Idle
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Sheet.