Ports And Attributes; Clk_Correct_Use - Xilinx RocketIO User Manual

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Clock Recovery
Similarly, if RXUSRCLK is slower than RXRECCLK, the buffer fills up over time. The clock
correction logic corrects for this by incrementing the read pointer to skip over a removable
byte sequence that need not appear in the final FPGA core byte stream. This is shown in the
bottom buffer,
represented by the dashed pointer. This accelerates the emptying of the buffer, preventing
its overflow. The transceiver design skips a single byte sequence, when necessary, to
partially empty a buffer. If attribute CLK_COR_REPEAT_WAIT is 0, the transceiver can
also skip four consecutive removable byte sequences in one step, to further empty the
buffer when necessary.
These operations require the clock correction logic to recognize a byte sequence that can be
freely repeated or omitted in the incoming data stream. This sequence is generally an IDLE
sequence, or other sequence comprised of special values that occur in the gaps separating
packets of meaningful data. These gaps are required to occur sufficiently often to facilitate
the timely execution of clock correction.
The clock correction logic has the ability to remove up to four IDLE sequences during a
clock correction. How many IDLEs are removed depends on several factors, including
how many IDLEs are received and whether CLK_COR_KEEP_IDLE is TRUE or FALSE.
For example, if three IDLEs are received and CLK_COR_KEEP_IDLE is set to TRUE, at
least one IDLE sequence must remain after clock correction has been completed. This
limits the clock correction logic to remove only two of the three IDLE sequences. If
CLK_COR_KEEP_IDLE is FALSE, then all three IDLEs can be removed.
Table 2-14
inherent stability of REFCLK, and the number of bytes allowed between clock correction
sequences.
Table 2-14: Data Bytes Allowed Between Clock Corrections as a Function of
REFCLK Stability and IDLE Sequences Removed
Notes:
1. All numbers are approximate.
2. IDLE = the defined clock correction sequence.

Ports and Attributes

CLK_CORRECT_USE

This attribute controls whether the PCS will repeat/skip the clock correction sequences
(CCS) from the elastic buffer to compensate for differences between the clock recovered
from serial data and the reference clocks. When this attribute is set to TRUE, the clock
correction is enabled. If set to FALSE, clock correction is disabled. When clock correction is
disabled, RXRECCLK must drive the receive logic in the fabric. Otherwise, the elastic
buffer may over/underflow.
RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
Figure 2-20, where the solid read pointer increments to the value
illustrates the relationship between the number of IDLE sequences removed, the
Bytes Allowed Between Clock Correction Sequences
REFCLK Remove 1 IDLE
Stability Sequence:
100 ppm 5,000
50 ppm 10,000
20 ppm 25,000
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(2)
Remove 2 IDLE Remove 3 IDLE
Sequences: Sequences:
10,000
20,000
50,000
(1)
Remove 4 IDLE
Sequences:
15,000 20,000
30,000 40,000
75,000 100,000
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