Rxloopfilterc[1:0]; Table C-24: Vco Divider Ratio Definition; Table C-25: Brefclk Divider Ratio Definition; Table C-26: Rxloopfilterc[1:0] Definition - Xilinx RocketIO X User Manual

Register Definition
Table C-23: RXRECCLK Divider Ratio Definition (Continued)

Table C-24: VCO Divider Ratio Definition

Table C-25: BREFCLK Divider Ratio Definition

RXLOOPFILTERC[1:0]

RXLOOPFILTERC[1:0] selects the receiver PLL filter capacitor setting. The default is
primitive dependent. The receiver loop filter capacitor selection is as follows:

Table C-26: RXLOOPFILTERC[1:0] Definition

RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
RXDIVRATIO[7:4]
0111
1000
1001
1010
1011
1100
1101
1110
1111
RXDIVRATIO[12]
0
1
RXDIVRATIO[13] BREFCLK Divider (Phase Detector)
0
1
RXLOOPFILTERC[1:0]
00
01
10
11
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Divider
Reserved
÷ 16
÷ 16.5
÷ 20
Reserved
Reserved
Reserved
Reserved
Reserved
VCO Divider
÷ 1
÷ 2
÷ 1
÷ 2
RX Filter Capacitor
15 pF
30 pF
30 pF
45 pF
R
157