Appendix A: Rocketio X Transceiver Timing Model; Table A-1: Rocketio X Clock Descriptions - Xilinx RocketIO X User Manual

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RocketIO X Transceiver Timing Model
This appendix explains the timing parameters associated with the RocketIO X™
transceiver core. It is intended to be used in conjunction with Module 3 of the Virtex-II Pro
data sheet (DS083) and the Timing Analyzer (TRCE) report from Xilinx software. For
specific timing parameter values, refer to the data sheet.
There are many signals entering and exiting the RocketIO X core. (Refer to
model presented in this section treats the RocketIO X core as a "black box." Propagation
delays internal to the RocketIO X core logic are ignored. Signals are characterized with
setup and hold times for inputs, and with clock to valid output times for outputs.
There are seven clocks associated with the RocketIO X core, but only three of these clocks—
RXUSRCL, RXUSRCLK2, and TXUSRCLK2—have I/Os that are synchronous to them. The
following table gives a brief description of all of these clocks. For an in-depth discussion of
clocking the RocketIO X core, refer to

Table A-1: RocketIO X Clock Descriptions

RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
CLOCK SIGNAL
BREFCLKPIN & Main reference clock for RocketIO X transceiver.
BREFCLKNIN
REFCLK High-quality reference clock driving transmission (reading TX
FIFO, and multiplied for parallel/serial conversion) and clock
recovery. REFCLK frequency is accurate to ± 100 ppm. This clock
originates off the device, is routed through fabric interconnect,
and is selected by the REFCLKSEL.
TXOUTCLK Synthesized Clock from RocketIO X transmitter. This clock can be
scaled (e.g., for 64B/66B) relative to BREFCLK, depending upon
the specific operating mode of the transmitter.
TXUSRCLK Clock used for writing the TX buffer. Frequency-locked to
REFCLK.
TXUSRCLK2 Clocks transmission data and status and reconfiguration data
between the transceiver and the FPGA fabric. Relationship
between TXUSRCLK2 and TXUSRCLK depends on width of
transmission data path.
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Chapter 2, "Digital Design Considerations."
DESCRIPTION
Appendix A
Figure A-2.) The
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