Enpcommaalign; Enmcommaalign; Enpcommaalign Enmcommaalign - Xilinx RocketIO User Manual

SERDES Alignment
uncertainty exists in the 4-byte mode as to which byte will contain the comma, as shown in
Table
Table 2-12: Possible Locations of Comma Character

ENPCOMMAALIGN,

ENMCOMMAALIGN

These two alignment ports control how the PMA aligns incoming serial data. It can align on a
minus-comma (negative disparity), a plus-comma (positive disparity), both, or neither if comma
alignment is not desired. These signals are latched inside the transceiver with RXRECCLK.
Care must be taken not to de-assert these signals at the improper time. Comma detection may be
vulnerable to spurious realignment if RXRECCLK occurs at the wrong time. To avoid this problem,
ENPCOMMAALIGN and ENMCOMMAALIGN should be passed through a flip-flop that is
clocked with RXRECCLK. These flip-flops should be located near the MGT, and RXRECCLK
should use local interconnect (not global clock resources) to reduce skew. For both top and bottom
edges, the best slices to use are in the CLB immediately to the left of the transceiver, next to the
bottom of the transceiver. For the top side of the chip, this is the fourth CLB row; for the bottom
side, the bottom CLB row. For example, for the XC2VP7, here are the best slices to use for two of
the transceivers:
•
•
This must be done for each MGT.
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
2-12. See "Receive Data Path 32-bit Alignment"
ALIGN_COMMA_MSB:
TRUE
FALSE
For GT_X0Y1 (top edge), the best slices are SLICE_X15Y72 and SLICE_X15Y73.
For GT_X0Y0 (bottom edge), the best slices are SLICE_X14Y0 and SLICE_X14Y1.
PCOMMA_CONTROL
MCOMMA_CONTROL
Figure 2-17: Synchronizing Comma Align Signals to RXRECCLK
www.xilinx.com
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for more details on this case.
Data Path Width:
1 byte 2 bytes
[7:0] [15:8] [7:0]
√ √
√ √ √
Figure 2-17 shows this recommendation.
D Q
D Q
4 bytes
[31:24] [23:16] [15:8]
√ √
√ √ √
GT_std_
*
ENPCOMMAALIGN
RXRECCLK
ENMCOMMAALIGN
UG024_39_013103
R
[7:0]
√
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