Quad-Core Intel® Xeon® Processor 5300 Series Features - Intel E5310 - Xeon 1.6 GHz 8M L2 Cache 1066MHz FSB LGA771 Active Quad-Core Processor Datasheet

Monitor software enabling multiple, independent software environments inside a single
platform. Further details on Intel Virtualization Technology can be found at
http://developer.intel.com/technology/virtualization/index.htm.
The Quad-Core Intel® Xeon® Processor 5300 Series are intended for high performance
server and workstation systems. The processors support a Dual Independent Bus (DIB)
architecture with one processor on each bus, up to two processor sockets in a system.
The DIB architecture provides improved performance by allowing increased FSB speeds
and bandwidth. The processors will be packaged in an FC-LGA6 Land Grid Array
package with 771 lands for improved power delivery. It utilizes a surface mount
LGA771 socket that supports Direct Socket Loading (DSL).
Table 1-1. Quad-Core Intel® Xeon® Processor 5300 Series Features
# of Processor
Cores
4
Quad-Core Intel® Xeon® Processor 5300 Series based platforms implement
independent core voltage (V
voltage (V
utilizes power delivery guidelines specified by VRM/EVRD 11.0 and its associated load
line (see Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down
(EVRD) 11.0 Design Guidelines for further details). VRM/EVRD 11.0 will support the
power requirements of all frequencies of the processors including Flexible Motherboard
Guidelines (FMB) (see
guidelines for implementation details.
The Quad-Core Intel® Xeon® Processor 5300 Series support either 1333 or 1066 MHz
Front Side Bus operation. The FSB utilizes a split-transaction, deferred reply protocol
and Source-Synchronous Transfer (SST) of address and data to improve performance.
The processor transfers data four times per bus clock (4X data transfer rate, as in AGP
4X). Along with the 4X data bus, the address bus can deliver addresses two times per
bus clock and is referred to as a 'double-clocked' or a 2X address bus. In addition, the
Request Phase completes in one clock cycle. Working together, the 4X data bus and 2X
address bus provide a data bus bandwidth of up to 10.66 GBytes (1333 MHz) or 8.5
GBytes (1066 MHz) per second. The FSB is also used to deliver interrupts.
Signals on the FSB use Assisted Gunning Transceiver Logic (AGTL+) level voltages.
Section 2.1
details are fully described in the appropriate platform design guidelines (refer to
Section 1.3).
10
L1 Cache (per
core)
32 KB instruction
32 KB data
) power planes for each processor. FSB termination
CC
) is shared and must connect to all FSB agents. The processor core voltage
TT
Section 2.13.1). Refer to the appropriate platform design
contains the electrical specifications of the FSB while implementation
L2 Advanced Front Side Bus
Transfer Cache Frequency
4MB Shared L2 1333 MHz
Cache per die
1066 MHz
8MB Total Cache
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Introduction
Package
FC-LGA6
771 Lands