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Intel CORE I7-900 DEKSTOP - SPECIFICATION Specification
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Intel CORE I7-900 DEKSTOP - SPECIFICATION Specification

Intel CORE I7-900 DEKSTOP - SPECIFICATION Specification

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®
Intel
Core™ i7-900 Desktop
Processor Extreme Edition Series
and Intel
Processor Series
Specification Update
April 2010
®
Notice: Intel
Core™ i7-900 Desktop Processor Extreme Edition Series and Intel® Core™ i7-
900 Desktop Processor Series may contain design defects or errors known as errata which may
cause the product to deviate from published specifications. Current characterized errata are
documented in this Specification Update.
®
Core™ i7-900 Desktop
Document Number: 320836-015

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Summary of Contents for Intel CORE I7-900 DEKSTOP - SPECIFICATION

  • Page 1 ® Notice: Intel Core™ i7-900 Desktop Processor Extreme Edition Series and Intel® Core™ i7- 900 Desktop Processor Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
  • Page 2 Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

  • Page 3: Table Of Contents

    Contents Preface ..........................5 Summary Tables of Changes ....................7 Identification Information ...................... 17 Errata..........................19 Specification Changes ......................66 Specification Clarifications ..................... 67 Documentation Changes ......................68 ® Intel Core™ i7 processor Specification Update...
  • Page 4 -004 May 13 2009 • Deleted Erratum AAJ105 and replaced with new erratum • Added Errata AAJ106-AAJ108 • Included Intel® Core™ i7-975 processor Extreme Edition and -005 June 3 2009 Intel® Core™ i7-950 processor • Added Errata AAJ109 - AAJ117...

  • Page 5: Preface

    ® Intel Core™ i7-900 Desktop Processor Series Datasheet Volume 2 ts/320835.pdf Related Documents Document Title Document Number/Location ® AP-485, Intel Processor Identification and the CPUID Instruction http://www.intel.com/des ign/processor/applnots/2 41618.htm http://www.intel.com/des ® Intel 64 and IA-32 Architectures Software Developer’s Manual ign/processor/specupdt/2 Documentation Changes 52046.htm...
  • Page 6 ® Intel 64 and IA-32 Intel Architecture Optimization Reference Manual Nomenclature ® Errata are design defects or errors. These may cause the Intel Core™ i7 processor ® Extreme Edition and Intel Core™ i7 processor behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices.

  • Page 7: Summary Tables Of Changes

    Change bar to left of table row indicates this erratum is either new or modified from the previous version of the document. Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that are used in Intel’s microprocessor Specification Updates: ®...
  • Page 8 Core™ Solo processor on 65nm process ® ® AF = Dual-Core Intel Xeon processor LV ® ® AG = Dual-Core Intel Xeon processor 5100 series AH = Intel® Core™2 Duo/Solo Processor for Intel® Centrino® Duo Processor Technology ® Intel Core™ i7 processor Specification Update...
  • Page 9 Summary Tables of Changes AI = Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor E6000 and E4000 sequence ® ® AJ = Quad-Core Intel Xeon processor 5300 series ® AK = Intel Core™2 Extreme quad-core processor QX6000 sequence and Intel®...
  • Page 10 Memory Aliasing of Code Pages May Cause Unpredictable System Behavior No Fix AAJ22 Delivery Status of the LINT0 Register of the Local Vector Table May be Lost No Fix AAJ23 Performance Monitor Event SEGMENT_REG_LOADS Counts Inaccurately No Fix ® Intel Core™ i7 processor Specification Update...
  • Page 11 Floating-Point Error (#MF) AAJ42 Incorrect TLB Translation May Occur After Exit From C6 Fixed USB 1.1 ISOCH Audio Glitches with Intel® QuickPath Interconnect Locks AAJ43 Fixed and Deep C-States Stack Pointer May Become Incorrect In Loops With Unbalanced Push and...
  • Page 12 Infinite Stream of Interrupts May Occur if an ExtINT Delivery Mode AAJ70 No Fix Interrupt is Received while All Cores in C6 AAJ71 Two xAPIC Timer Event Interrupts May Unexpectedly Occur No Fix ® Intel Core™ i7 processor Specification Update...
  • Page 13 PEBS Field “Data Linear Address” is Not Sign Extended to 64 Bits No Fix AAJ76 Core C6 May Not Operate Correctly in the Presence of Bus Locks No Fix Intel® Turbo Boost Technology May be Limited Immediately After Package AAJ77 No Fix C-state Exit with QPI L1 Mode Disabled AAJ78 APIC Error “Received Illegal Vector”...
  • Page 14 Triggering of the Monitor Hardware BIST Results May be Additionally Reported After a GETSEC[WAKEUP] or AAJ115 No Fix INIT-SIPI Sequence AAJ116 Pending x87 FPU Exceptions (#MF) May be Signaled Earlier Than Expected No Fix ® Intel Core™ i7 processor Specification Update...
  • Page 15 FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access AAJ138 Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in No Fix 64-bit Mode AAJ139 IO_SMI Indication in SMRAM State Save Area May Be Lost No Fix ® Intel Core™ i7 processor Specification Update...
  • Page 16 SPECIFICATION CHANGES There are no Specification Changes in this Specification Update revision. SPECIFICATION CLARIFICATIONS AAJ1 Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation DOCUMENTATION CHANGES There are no Documentation Changes in this Specification Update revision. ® Intel Core™ i7 processor Specification Update...

  • Page 17: Identification Information

    The Extended Family, bits [27:20] are used in conjunction with the Family Code, specified in bits [11:8], to indicate whether the processor belongs to the Intel386, Intel486, Pentium, Pentium Pro, Pentium 4, Intel® Core™ processor family or Intel® Core i7 family.
  • Page 18 2.66 / 4.80/ 1066 1/1/1/2 NOTES: Although these units are factory-configured for 1333 MHz integrated memory controller frequency, Intel does not support operation beyond 1066 MHz; however, this processor has additional support to override the integrated memory controller frequency. ®...

  • Page 19: Errata

    The MONITOR instruction only functions correctly if the specified linear address range is of the type write- back. CLFLUSH flushes data from the cache. Intel has not observed this erratum with any commercially available software.
  • Page 20 #GP fault (general protection exception). Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP fault. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
  • Page 21 #GP fault may not match the non-canonical address that caused the fault. Implication: Operating systems may observe a #GP fault being serviced before higher priority Interrupts and Exceptions. Intel has not observed this erratum on any commercially available software. Workaround: None identified.
  • Page 22 V86 mode before continuing. If the exception did occur in V86 mode, the exception may be directed to the general-protection exception handler. For the steppings affected, see the Summary Table of Changes. Status: ® Intel Core™ i7 processor Specification Update...
  • Page 23 • #DB is signaled before the pending higher priority #MF (Interrupt 16) • #DB is generated twice on the same instruction Workaround: None identified. For the steppings affected, see the Summary Table of Changes. Status: ® Intel Core™ i7 processor Specification Update...
  • Page 24 Manual, Vol. 1, Basic Architecture, for information on the usage of the ENTER instructions. This erratum is not expected to occur in ring 3. Faults are usually processed in ring 0 and stack switch occurs when transferring to ring 0. Intel has not observed this erratum on any commercially available software.
  • Page 25 Whenever an Level 3 cache fill conflicts with another request's address, the Problem: miss to fill occupancy counter, UNC_GQ_ALLOC.RT_LLC_MISS (Event 02H), will provide erroneous results. Implication: The Performance Monitoring UNC_GQ_ALLOC.RT_LLC_MISS event may count a value higher than expected. The extent to which the value ® Intel Core™ i7 processor Specification Update...
  • Page 26 Workaround: Code pages should not be mapped with uncacheable and cacheable memory types at the same time. For the steppings affected, see the Summary Table of Changes. Status: ® Intel Core™ i7 processor Specification Update...
  • Page 27 • There is a pending interrupt which is masked with the interrupt enable flag (IF) Implication: Due to this erratum, the Delivery Status bit of the LINT0 Register will unexpectedly not be set. Intel has not observed this erratum with any commercially available software or system.
  • Page 28 Stack Segment and Stack Pointer. If MOV SS/POP SS is not followed by a MOV [r/e]SP, [r/e]BP, there may be a mismatched Stack Segment and Stack Pointer on any exception. Intel has not observed this erratum with any commercially available software or system.
  • Page 29 Workaround: None identified. For the steppings affected, see the Summary Table of Changes. Status: AAJ28. Intel® QuickPath Memory Controller tTHROT_OPREF Timings May be Violated During Self Refresh Entry During self refresh entry, the memory controller may issue more refreshes Problem: than permitted by tTHROT_OPREF (bits 29:19 in MC_CHANNEL_{0,1,2}_REFRESH_TIMING CSR).
  • Page 30 Thermal Monitor disable. This condition will only correct itself once the processor reaches its TCC activation temperature again. Implication: Since Intel requires that Thermal Monitor be enabled in order to be operating within specification, this erratum should never be seen during normal operation.
  • Page 31 Implication: Due to this erratum, the processor core may not wake up from S1 state. Workaround: It is possible for the BIOS to contain a workaround for this erratum. For the steppings affected, see the Summary Table of Changes. Status: ® Intel Core™ i7 processor Specification Update...
  • Page 32 Problem: MASKMOVQ) which cause memory access faults (#GP, #SS, #PF, or #AC), may incorrectly update the x87 FPU tag word register. This erratum will occur when the following additional conditions are also met. ® Intel Core™ i7 processor Specification Update...
  • Page 33 Workaround: It is possible for the BIOS to contain a workaround for this erratum. For the steppings affected, see the Summary Table of Changes. Status: AAJ43. USB 1.1 ISOCH Audio Glitches with Intel® QuickPath Interconnect Locks and Deep C-States ® Intel Core™...
  • Page 34 Errata An interrupt directed at a Core in C3 or C6 that collides with an Intel® Problem: QuickPath Interconnect Lock sequence may delay ISOCH transactions to DRAM long enough to underrun USB 1.1 buffers. Implication: USB 1.1 Audio devices may have audio glitches.
  • Page 35 Bits 53:50 of the IA32_VMX_BASIC MSR report the memory type that the Problem: processor uses to access the VMCS and data structures referenced by pointers in the VMCS. Due to this erratum, a VMX access to the VMCS or referenced ® Intel Core™ i7 processor Specification Update...
  • Page 36 VM entry may operate as if CS.D=0. Implication: Instructions executed after VM entry may use the wrong operation size. Intel has not observed this erratum with any commercially available system. Workaround: It is possible for the BIOS to contain a workaround for this erratum.
  • Page 37 MOVNTDQA From WC Memory May Pass Earlier Locked Instructions An execution of MOVNTDQA that loads from WC (write combining) memory Problem: may appear to pass an earlier locked instruction to a different cache line. ® Intel Core™ i7 processor Specification Update...
  • Page 38 Implication: Memory ordering may be violated. Intel has not observed this erratum with any commercially available software. Workaround: Software should ensure pages are not being actively used before requesting their memory type be changed.
  • Page 39 Running with Write Major Mode Disabled May Lead to a System Hang With write major mode disabled, reads will be favored over writes and under Problem: certain circumstances this can lead to a system hang. ® Intel Core™ i7 processor Specification Update...
  • Page 40 64-bit mode from outside 64-bit mode, bits 63:32 of the RIP value pushed on the stack may be cleared to 0: 4. A non-maskable interrupt (NMI); 5. A machine-check exception (#MC); 6. A page fault (#PF) during instruction fetch; or ® Intel Core™ i7 processor Specification Update...
  • Page 41 Implication: Due to this erratum, a livelock may occur that can only be terminated by a processor reset. Intel has not observed this erratum with any commercially available software.
  • Page 42 (EFLAGS.IF=1). However, the pending interrupt event will not be cleared. Implication: Due to this erratum, an infinite stream of interrupts will occur on the core servicing the external interrupt. Intel has not observed this erratum with any commercially available software/system. Workaround: None identified.
  • Page 43 Implication: EOI transactions and interrupts may be blocked when core C6 is used during interrupt service routines. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
  • Page 44 If the processor is resident in package C3 or C6 for greater than 100ms and Problem: QPI (Intel® QuickPath Interconnect) link L1 mode is disabled, it is possible for Turbo Boost input parameters to be incorrect. As a result, on exit from the package C-state the processor may not enter Turbo Boost for up to 2 ms.
  • Page 45 SS,r/m (MOV to the stack segment selector) or POP SS (POP stack segment selector) instruction will not clear the changes in DR6 because data breakpoints are not taken immediately after a MOV SS,r/m or POP SS ® Intel Core™ i7 processor Specification Update...
  • Page 46 Uncore. Workaround: Program any one of the Uncore general performance monitor counters with a valid performance monitor event and enable the event by setting the local ® Intel Core™ i7 processor Specification Update...
  • Page 47 Including Self) or 11B (All Excluding Self). Implication: When this erratum occurs, cores which are in a sleep state may not wake up to handle the broadcast IPI. Intel has not observed this erratum with any commercially available software. ®...
  • Page 48 Unexpected QPI Link Behavior May Occur When a CRC Error Happens During L0s When a QPI (Intel® QuickPath Interconnect) agent requests L0s entry while a Problem: CRC (Cyclic Redundancy Check) error occurs during this flit or on the flit just before it, the requesting QPI agent may enter L0s and turn its drivers off.
  • Page 49 Implication: Increased Isoch latencies may cause perturbations in system operation. (ex: audio glitches. Workaround: It is possible for the BIOS to contain a workaround for this erratum. For the steppings affected, see the Summary Table of Changes. Status: ® Intel Core™ i7 processor Specification Update...
  • Page 50 Implication: None identified. Although the EFLAGS value saved by an affected event (a page fault or an EPT-induced VM exit) may contain incorrect arithmetic flag values, Intel has not identified software that is affected by this erratum. This erratum will have no further effects once the original instruction ®...
  • Page 51 MC_CHANNEL_{0,1,2}_MC_DIMM_INIT_CMD.DO_ZQCL field are not in increasing populated DDR3 rank order. Workaround: It is possible for Intel provided BIOS reference code to contain a workaround for this erratum. Please refer to the latest version of BIOS Memory Reference Code and release notes.
  • Page 52 Corrected Errors With a Yellow Error Indication May be Overwritten by Other Corrected Errors A corrected cache hierarchy data or tag error that is reported with Problem: IA32_MCi_STATUS.MCACOD (bits [15:0]) with value of ® Intel Core™ i7 processor Specification Update...
  • Page 53 (e.g., with bit 0 clear in the page-fault error code, indicating that the fault was caused by a not-present page). ® Intel Core™ i7 processor Specification Update...
  • Page 54 Errata Implication: Software may see an unexpected page fault that indicates that there is no translation for the page. Intel has not observed this erratum with any commercially available software or system. Workaround: Software should not update the paging structures with a string instruction that accesses pages mapped the modified paging structures.
  • Page 55 (that is part of the C3, C6 or S3 entry). Implication: tRP timing violation may occur on DRAM entry to self refresh while entering package C3, C6 or S3 states. Intel has not observed this erratum with any commercially available software. This condition has only been produced in simulation and affects a pre-charge to banks already pre-charged.
  • Page 56 Implication: Due to this erratum, updates to segment descriptors may not be preserved. Intel has not observed this erratum with any commercially available software or system. Workaround: None identified.
  • Page 57 Problem: Due to this erratum, if an instruction that triggers #MF is executed while Enhanced Intel SpeedStep® Technology transitions, Intel® Turbo Boost Technology transitions, or Thermal Monitor events occur, the pending #MF may be signaled before pending interrupts are serviced.
  • Page 58 However, if one of the counters set to generate an interrupt on overflow is the IA32_FIXED_CTR2 (MSR 30BH) counter, multiple interrupts may be generated when the IA32_FIXED_CTR2 overflows at the same time as any of the other performance counters. ® Intel Core™ i7 processor Specification Update...
  • Page 59 Problem: (Branch Trace Message) or BTS (Branch Trace Store) may be incorrect for the first branch after an EIST (Enhanced Intel® SpeedStep Technology) transition, T-states, C1E (C1 Enhanced), or Adaptive Thermal Throttling. Implication: When the LBRs, BTM or BTS are enabled, some records may have incorrect branch “From”...
  • Page 60 This erratum only occurs when IA32_FIXED_CTR0 overflows and the processor and counter are configured as follows: • Intel® Hyper-Threading Technology is enabled • IA32_FIXED_CTR0 local and global controls are enabled • IA32_FIXED_CTR0 is set to count events only on its own thread (IA32_FIXED_CTR_CTRL MSR (38DH) bit [2] = ‘0).
  • Page 61 Monitor events STORE_BLOCKS.NOT_STA and STORE_BLOCKS.STA may indicate a higher occurrence of loads blocked by stores than have actually occurred. If Intel Hyper-Threading Technology is enabled, the counts of loads blocked by stores may be unpredictable and they could be higher or lower than the correct count.
  • Page 62 Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be lower than expected. The degree of undercounting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially available software.
  • Page 63 In a complex set of internal conditions when the processor exits from Core C6 Problem: state, it is possible that an interrupt may be dropped. Implication: Due to this erratum, an interrupt may be dropped. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
  • Page 64 Implication: This erratum may cause unpredictable system behavior. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
  • Page 65 Implication: Due to this erratum, the FP Data Operand Pointer may be incorrect. Wrapping an 80-bit FP load around a 4-Gbyte boundary in this way is not a normal programming practice. Intel has not observed this erratum with any commercially available software.

  • Page 66: Specification Changes

    Specification Changes The Specification Changes listed in this section apply to the following documents: ® ® • Intel Core™ i7 Processor Extreme Edition and Intel Core™ i7 Processor Datasheet ® • Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture ®...

  • Page 67: Specification Clarifications

    64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide will be modified to include the presence of page table structure caches, such as the page directory cache, which Intel processors implement. This information is needed to aid operating systems in managing page table structure invalidations properly.

  • Page 68: Documentation Changes

    Documentation Changes The Documentation Changes listed in this section apply to the following documents: ® ® • Intel Core™ i7 Processor Extreme Edition and Intel Core™ i7 Processor Datasheet ® • Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture ®...