Instruction Address Compare Registers (Iac1-Iac4); Data Address Compare Registers (Dac1-Dac2); Figure 12-7. Instruction Address Compare Registers (Iac1-Iac4) - IBM PowerPC 405GP User Manual

11 IDE
Imprecise Debug Event
o
No circumstance that would cause a
debug event (if MSR[DE]
=
1) occurred
1 A debug event would have occurred, but
debug exceptions were disabled
(MSR[DE]
=
1)
12 IA3 IAC3 Debug Event
o
Event did not occur
1 Event occurred
13 IA4 IAC4 Debug Event
o
Event did not occur
1 Event occurred
14:21 Reserved
22:23 MRR Most Recent Reset This field is set to a value, indicating the
00 No reset has occurred since last type of reset, when a reset occurs.
cleared by software.
01 Core reset
10 Chip reset
11 System reset
24:31 Reserved
12.9.3 Instruction Address Compare Registers (IAC1-IAC4)
The PPC405GP can take a debug event upon an attempt to execute an instruction from an address.
The address, which must be word-aligned, is defined in an lAC register. The OBCRO[IA 1, IA2] fields of
OBCRO controls the instruction address compare (lAC) debug event.
1
0
29130311
Figure 12-7. Instruction Address Compare Registers (IAC1-IAC4)
0:29 Instruction Address Compare word Omit two low-order bits of complete
address address.
30:31 Reserved
.
12.9.4 Data Address Compare Registers (DAC1-DAC2)
The PPC405GP can take a debug event upon storage or cache references to addresses specified in
the OAC registers. The specified addresses in the OAC registers are EAs of operands of storage
12-14
PPC405GP User's Manual Preliminary