Register 18: Phy Address Register; Register 19: 100Base-Tx Receive False Carrier Counter Bit Definitions; Register 20: 100Base-Tx Receive Disconnect Counter Bit Definitions; Register 21: 100Base-Tx Receive Error Frame Counter Bit Definitions - Intel GD82559ER Datasheet

GD82559ER — Networking Silicon
Bit(s)
0
9.3.3

Register 18: PHY Address Register

Bit(s)
15:5
4:0
9.3.4 Register 19: 100BASE-TX Receive False Carrier Counter Bit
Definitions
Bit(s)
15:0
9.3.5

Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions

Bit(s)
15:0
9.3.6 Register 21: 100BASE-TX Receive Error Frame Counter Bit
Definitions
Bit(s)
15:0
9.3.7

Register 22: Receive Symbol Error Counter Bit Definitions

Bit(s)
15:0
70
Name
Jabber Function 1 = Jabber disabled
Disable
0 = Normal Jabber operation
Name
Reserved These bits are reserved and should be set to a
constant '0'
PHY Address These bits are set to the PHY's address, 00001b.
Name
Receive False These bits are used for the false carrier counter.
Carrier
Name
Disconnect Event This field contains a 16-bit counter that increments for
each disconnect event. The counter freezes when full
and self-clears on read
Name
Receive Error This field contains a 16-bit counter that increments
Frame once per frame for any receive error condition (such
as a symbol error or premature end of frame) in that
frame. The counter freezes when full and self-clears
on read.
Name
Symbol Error This field contains a 16-bit counter that increments for
Counter each symbol error. The counter freezes when full and
self-clears on read.
In a frame with a bad symbol, each sequential six bad
symbols count as one.
Description
Description
Description
Description
Description
Description
Default R/W
0 RW
Default R/W
0 RO
1 RO
Default R/W
-- RO
SC
Default R/W
-- RO
SC
Default R/W
-- RO
SC
Default R/W
-- RO
SC
Datasheet