Iolimit6 - I/O Limit Address; Iobase6 - I/O Base Address Register; Iolimit6 - I/O Limit Address Register - Intel I5-520E - DATASHEET ADDENDUM Datasheet

Processor Configuration Registers
Table 35.

IOBASE6 - I/O Base Address Register

Bit Access Default
Value
7:4 RW
3:0 RO
6.2.13

IOLIMIT6 - I/O Limit Address

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register controls the CPU to PCI Express-G I/O access routing based on the
following formula:
IO_BASE=< address =<IO_LIMIT
Only upper 4 bits are programmable. For the purpose of address decode address bits
A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range is at
the top of a 4-KB aligned address block.
Table 36.

IOLIMIT6 - I/O Limit Address Register

Default
Bit Access
7:4 RW
3:0 RO
April 2010
Document Number: 323178-002
RST/
PWR
Fh Core I/O Address Base (IOBASE)
Corresponds to A[15:12] of the I/O addresses passed by bridge 1
to PCI Express-G.
BIOS must not set this register to 00h otherwise 0CF8h/0CFCh
accesses is forwarded to the PCI Express hierarchy associated
with this device.
0h Core Reserved
RST/
Value PWR
0h Core I/O Address Limit (IOLIMIT)
Corresponds to A[15:12] of the I/O address limit of Device 6.
Devices between this upper limit and IOBASE6 is passed to the
PCI Express hierarchy associated with this device.
0h Core Reserved
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
Description
0/6/0/PCI
1Dh
00h
RO; RW
8 bits
Description
®
Celeron
®
Processor P4500, P4505 Series
Datasheet Addendum
93