Msi_Capid - Message Signaled Interrupts Capability Id; Mc - Message Control; Msi_Capid - Message Signaled Interrupts Capability Id Register; Mc - Message Control Register - Intel CELERON PROCESSOR P4505 - DATASHEET ADDENDUM Datasheet

Processor Configuration Registers
6.2.29

MSI_CAPID - Message Signaled Interrupts Capability ID

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
When a device supports MSI it can generate an interrupt request to the processor by
writing a predefined data item (a message) to a predefined memory address.
The reporting of the existence of this capability can be disabled by setting MSICH
(CAPL[0] @ 7Fh). In that case walking this linked list will skip this capability and
instead go directly from the PCI PM capability to the PCI Express capability.
Table 52.

MSI_CAPID - Message Signaled Interrupts Capability ID Register

Default
Bit Access
15:8 RO
7:0 RO
6.2.30

MC - Message Control

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
System software can modify bits in this register, but the device is prohibited from doing
so.
If the device writes the same message multiple times, only one of those messages is
guaranteed to be serviced. If all of them must be serviced, the device must not
generate the same message again until the driver services the earlier one.
Table 53. MC - Message Control Register (Sheet 1 of 2)
Bit Access Default
Value
15:8 RO
7 RO
® TM
Intel Core i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
August 2010
Document Number: 323178-003
RST/
Value PWR
A0h Core Pointer to Next Capability (PNC)
This contains a pointer to the next item in the capabilities list
which is the PCI Express capability.
05h Core Capability ID (CID)
Value of 05h identifies this linked list item (capability structure)
as being for MSI registers.
RST/
PWR
00h Core Reserved
0b Core 64-bit Address Capable (64AC)
hard wired to 0 to indicate that the function does not implement
the upper 32 bits of the Message Address register and is
incapable of generating a 64-bit memory address.
This may need to change in future implementations when
addressable system memory exceeds the 32-b/4-GB limit.
0/6/0/PCI
90-91h
A005h
RO
16 bits
Description
0/6/0/PCI
92-93h
0000h
RO; RW
16 bits
Description
® ®
Celeron Processor P4505, U3405 Series
Datasheet Addendum
109