Pbusn6 - Primary Bus Number; Sbusn6 - Secondary Bus Number; Pbusn6 - Primary Bus Number Register; Sbusn6 - Secondary Bus Number Register - Intel I5-520E - DATASHEET ADDENDUM Datasheet

Processor Configuration Registers
6.2.9

PBUSN6 - Primary Bus Number

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register identifies that this "virtual" Host-PCI Express bridge is connected to PCI
Bus 0.
Table 32.

PBUSN6 - Primary Bus Number Register

Bit Access Default
7:0 RO
6.2.10

SBUSN6 - Secondary Bus Number

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register identifies the bus number assigned to the second bus side of the "virtual"
bridge, i.e., to PCI Express-G. This number is programmed by the PCI configuration
software to allow mapping of configuration cycles to PCI Express-G.
Table 33.

SBUSN6 - Secondary Bus Number Register

Bit Access Default
7:0 RW
April 2010
Document Number: 323178-002
RST/
Value PWR
00h Core Primary Bus Number (BUSN)
Configuration software typically programs this field with the
number of the bus on the primary side of the bridge. Since
Device 6 is an internal device and its primary bus is always 0,
these bits are read only and are hard wired to 0.
RST/
Value PWR
00h Core Secondary Bus Number (BUSN)
This field is programmed by configuration software with the bus
number assigned to PCI Express-G.
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
0/6/0/PCI
18h
00h
RO
8 bits
Description
0/6/0/PCI
19h
00h
RW
8 bits
Description
®
Celeron
®
Processor P4500, P4505 Series
Datasheet Addendum
91