Output Ddr Primitive (Oddr); Oddr Vhdl And Verilog Templates - Xilinx SelectIO 7 Series User Manual

Output DDR Primitive (ODDR)

Figure 2-20
the same time.
attributes available and default values for the ODDR primitive.
X-Ref Target - Figure 2-20
Table 2-10: ODDR Port Signals
Q
C
CE
D1 and D2
S/R
Notes:
1. The ODDR primitive contains both set and reset pins. However only one can be used per ODDR. As a
Table 2-11: ODDR Attributes
DDR_CLK_EDGE
INIT
SRTYPE

ODDR VHDL and Verilog Templates

The Libraries Guide includes templates for instantiation of the ODDR module in VHDL
and Verilog.
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
shows the ODDR primitive block diagram. Set and Reset are not supported at
Table 2-10 lists the ODDR port signals.
Figure 2-20: ODDR Primitive Block Diagram
Port
Function
Name
Data output (DDR)
Clock input port
Clock enable port
Data inputs
(1)
Set/Reset
result, S/R is described instead of separate set and reset pins.
Attribute Name
Sets the ODDR mode of operation with
respect to clock edge
Sets the initial value for Q port
Set/Reset type with respect to clock (C)
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Table 2-11
D1 Q
ODDR
D2
CE
C
S/R
ug471_c2_18_022715
Description
ODDR register output.
The CLK pin represents the clock input pin.
CE represents the clock enable pin. When asserted Low,
this port disables the output clock on port Q.
ODDR register inputs.
Synchronous/Asynchronous set/reset pin. Set/Reset is
asserted High.
Description
OLOGIC Resources
describes the various
Possible Values
OPPOSITE_EDGE
(default), SAME_EDGE
0 (default), 1
ASYNC, SYNC (default)
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