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Figure 1-58
SSTL18, SSTL15, SSTL135, or SSTL12. In a specific circuit, all drivers and receivers must be
at the same voltage level (1.8V, 1.5V,1.35V, or 1.2V); they are not interchangeable. SSTL18
class-I is not available for bidirectional signaling. Also, SSTL18_II_DCI is the only available
DCI standard available for bidirectional signaling. The DCI versions of SSTL18_I, SSTL15,
SSTL135, and SSTL12 are only available for unidirectional signaling. Use the T_DCI
standards for bidirectional signaling of SSTL15, SSTL135, and SSTL12 with DCI
termination. The internal split-termination resistors are always present on SSTL18_II_DCI,
independent of whether the drivers are 3-stated.
X-Ref Target - Figure 1-58
External Termination
SSTL18_II
SSTL15(_R)
SSTL135(_R)
SSTL12
V
=
REF
0.9V for SSTL18_II
0.75V for SSTL15(_R)
0.675V for SSTL135(_R)
0.6V for SSTL12
DCI
R
SSTL18_II_DCI
R
V
REF
Figure 1-58: SSTL18, SSTL15, SSTL135, or SSTL12 Bidirectional Termination
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
shows a sample circuit illustrating a bidirectional termination technique for
V
=
TT
0.9V for SSTL18_II
0.75V for SSTL15(_R)
0.675V for SSTL135(_R)
0.6V for SSTL12
IOB
R P = Z 0 = 50Ω
IOB
V
= 1.8V
CCO
= 2Z 0 = 100Ω
VRN
= 2Z 0 = 100Ω
VRP
= 0.9V
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Supported I/O Standards and Terminations
V
=
TT
0.9V for SSTL18_II
0.75V for SSTL15(_R)
0.675V for SSTL135(_R)
0.6V for SSTL12
IOB
R P = Z 0 = 50Ω
Z 0
V
0.9V for SSTL18_II
0.75V for SSTL15(_R)
0.675V for SSTL135(_R)
0.6V for SSTL12
IOB
V
= 1.8V
CCO
R
= 2Z 0
VRN
= 100Ω
Z 0
R
= 2Z 0
VRP
= 100Ω
SSTL18_II
SSTL15(_R)
SSTL135(_R)
SSTL12
+
=
–
REF
SSTL18_II_DCI
+
–
V
= 0.9V
REF
ug471_c1_48_121214
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