Xilinx SelectIO 7 Series User Manual page 101

Table
availability, and DCI termination type for each 7 series FPGA supported I/O standard.
Table 1-56: DRIVE and SLEW Attributes, Bidirectional Buffers, and DCI Termination Type
I/O Standard
BLVDS_25
DIFF_HSTL_I
DIFF_HSTL_I_18
DIFF_HSTL_I_DCI
DIFF_HSTL_I_DCI_18
DIFF_HSTL_II
DIFF_HSTL_II_18
DIFF_HSTL_II_DCI
DIFF_HSTL_II_DCI_18
DIFF_HSTL_II_T_DCI
DIFF_HSTL_II_T_DCI_18
DIFF_HSUL_12
DIFF_HSUL_12_DCI
DIFF_MOBILE_DDR
DIFF_SSTL12
DIFF_SSTL12_DCI
DIFF_SSTL12_T_DCI
DIFF_SSTL135
DIFF_SSTL135_R
DIFF_SSTL135_DCI
DIFF_SSTL135_T_DCI
DIFF_SSTL15
DIFF_SSTL15_R
DIFF_SSTL15_DCI
DIFF_SSTL15_T_DCI
DIFF_SSTL18_I
DIFF_SSTL18_I_DCI
DIFF_SSTL18_II
DIFF_SSTL18_II_DCI
DIFF_SSTL18_II_T_DCI
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
1-56, summarizes the DRIVE and SLEW attribute options, bidirectional buffer
DRIVE (mA)
I/O Bank
Availability
Outputs
HR N/A
Both N/A
Both N/A
HP N/A
HP N/A
Both N/A
Both N/A
HP N/A
HP N/A
HP N/A
HP N/A
Both N/A
HP N/A
HR N/A
HP N/A
HP N/A
HP N/A
Both N/A
HR N/A
HP N/A
HP N/A
Both N/A
HR N/A
HP N/A
HP N/A
Both N/A
HP N/A
Both N/A
HP N/A
HP N/A
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Rules for Combining I/O Standards in the Same Bank
SLEW
Bidirectional
Buffers
Outputs
N/A Yes
SLOW, FAST No
SLOW, FAST No
SLOW, FAST No
SLOW, FAST No
SLOW, FAST Yes
SLOW, FAST Yes
SLOW, FAST Yes
SLOW, FAST Yes
SLOW, FAST Required
SLOW, FAST Required
SLOW, FAST Yes
SLOW, FAST Yes
SLOW, FAST Yes
SLOW, FAST Yes
SLOW, FAST No
SLOW, FAST Required
SLOW, FAST Yes
SLOW, FAST Yes
SLOW, FAST No
SLOW, FAST Required
SLOW, FAST Yes
SLOW, FAST Yes
SLOW, FAST No
SLOW, FAST Required
SLOW, FAST No
SLOW, FAST No
SLOW, FAST Yes
SLOW, FAST Yes
SLOW, FAST Required
(2)
DCI Type
(1)
Outputs Inputs
None None
None None
None None
None Split
None Split
None None
None None
Split Split
Split Split
None Split
None Split
None None
Driver None
None None
None None
None Split
None Split
None None
None None
None Split
None Split
None None
None None
None Split
None Split
None None
None Split
None None
Split Split
None Split
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