Xilinx SelectIO 7 Series User Manual page 122

Chapter 2: SelectIO Logic Resources
Figure 2-12
DELAY_SRC = IDATAIN) timing diagram.
X-Ref Target - Figure 2-12
Clock Event 1
On the rising edge of C, a reset is detected (LD is High), causing the output DATAOUT to
select tap 0 as the output from the 31-tap chain.
Clock Event 2
A pulse on CE and INC is captured on the rising edge of C. This indicates an increment
operation. The output changes without glitches from tap 0 to tap 1. See
Increment/Decrement
Clock Event 3
CE and INC are no longer asserted, thus completing the increment operation. The output
remains at tap 1 indefinitely until there is further activity on the LD, CE, or INC pins.
Figure 2-13
X-Ref Target - Figure 2-13
122
Send Feedback
shows an IDELAY (IDELAY_TYPE = VARIABLE, IDELAY_VALUE = 0, and
C
LD
CE
INC
DATAOUT
Figure 2-12: IDELAY Timing Diagram
Operation.
shows an IDELAY timing diagram in VAR_LOAD mode.
C
LD
INC
CE
CNTVALUEIN 5'b00010
CNTVALUEOUT
DATAOUT
Figure 2-13: IDELAY in VAR_LOAD Timing Diagram
www.xilinx.com
1 2 3
Tap 0
0 1 2
5'b00010
Tap 2
7 Series FPGAs SelectIO Resources User Guide
Tap 1
UG471_c2_10_011811
Stability after an
3
5'b01010
5'b00011 5'b01010
Tap 3 Tap 10
UG471_c2_11_011811
UG471 (v1.10) May 8, 2018