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•
Clock Event 4
At time T
this case) becomes valid-High, resetting the output register and reflected at the OQ output
at time T
Figure 2-22
X-Ref Target - Figure 2-22
Clock Event 1
•
•
Clock Event 2
•
Clock Event 9
At time T
synchronous reset in this case) becomes valid-high resetting ODDR register, reflected at the
OQ output at time T
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
At time T
before Clock Event 1, the output signal becomes valid-high at the D1
ODCK
input of the output register and is reflected at the OQ output at time T
Clock Event 1.
before Clock Event 4, the S/R signal (configured as synchronous reset in
OSRCK
after Clock Event 4.
RQ
illustrates the OLOGIC ODDR register timing.
1
2
3
CLK
T
ODCK
D1
T
D2
T
OOCECK
OCE
S/R
T
OCKQ
OQ
Figure 2-22: OLOGIC ODDR Register Timing Characteristics
At time T
before Clock Event 1, the ODDR clock enable signal becomes
OOCECK
valid-High at the OCE input of the ODDR, enabling ODDR for incoming data. Care
must be taken to toggle the OCE signal of the ODDR register between the rising edges
and falling edges of CLK as well as meeting the register setup-time relative to both
clock edges.
At time T
before Clock Event 1 (rising edge of CLK), the data signal D1 becomes
ODCK
valid-high at the D1 input of ODDR register and is reflected on the OQ output at time
T
after Clock Event 1.
OCKQ
At time T
before Clock Event 2 (falling edge of CLK), the data signal D2 becomes
ODCK
valid-high at the D2 input of ODDR register and is reflected on the OQ output at time
T
after Clock Event 2 (no change at the OQ output in this case).
OCKQ
before Clock Event 9 (rising edge of CLK), the S/R signal (configured as
OSRCK
after Clock Event 9 (no change at the OQ output in this case) and
RQ
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4
5
6
7
ODCK
T
OSRCK
(OPPOSITE_EDGE Mode)
OLOGIC Resources
after
OCKQ
8
9
10
11
T
RQ
ug471_c2_20_081215
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