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In VHDL, the VHDL constraint associated with the IOB primitive instantiation is declared
as follows:
In Verilog, the Verilog constraint is placed immediately before the module or instantiation
of the IOB primitive. The Verilog constraint is specified as follows:
7 Series FPGA I/O Resource VHDL/Verilog Examples
The VHDL and Verilog example syntaxes for instantiating 7 series FPGA I/O resources are
found in UG768: Xilinx 7 Series FPGA Libraries Guide for HDL Designs.
Supported I/O Standards and Terminations
The following sections provide an overview of the I/O standards and options supported
by all 7 series devices.
While most 7 series FPGA I/O supported standards specify a range of allowed voltages,
this chapter records typical voltage values only. Detailed information on each specification
can be found on the Electronic Industry Alliance JEDEC web site at
LVTTL (Low Voltage TTL)
Table 1-9: Available I/O Bank Type
LVTTL is a general-purpose EIA/JESD standard for 3.3V applications that uses a
single-ended CMOS input buffer and a push-pull output buffer. This standard requires a
3.3V output source voltage (V
(V
Sample circuits illustrating both unidirectional and bidirectional LVTTL termination
techniques are shown in
of source-series and parallel terminated topologies.
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
attribute VCCAUX_IO of {component_name |label_name}:
{component|label} is "{NORMAL|HIGH|DONTCARE}";
(* VCCAUX_IO = {NORMAL|HIGH|DONTCARE}*)
UCF and NCF Syntax
NET "net_name" VCCAUX_IO=(0|NORMAL|HIGH|DONTCARE);
INST "instance_name " VCCAUX_IO=(NORMAL|HIGH|DONTCARE);
HR
HP
Available
N/A
) or a termination voltage (V
REF
Figure 1-37
www.xilinx.com
Supported I/O Standards and Terminations
), but does not require the use of a reference voltage
CCO
). This standard is defined by JEDEC (JESD 8C.01).
TT
and
Figure
1-38. These two diagrams show examples
http://www.jedec.org.
51
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