Chapter 13: Ddr Sdram - Xilinx MIcroBlaze Development Spartan-3E 1600E Kit User Manual

R
DDR SDRAM
The MicroBlaze Development Kit board includes a 512 Mbit (32M x 16) Micron Technology
DDR SDRAM (MT46V32M16) with a 16-bit data interface, as shown in
DDR SDRAM interface pins connect to the FPGA's I/O Bank 3 on the FPGA. I/O Bank 3
and the DDR SDRAM are both powered by 2.5V, generated by an LTC3412 regulator from
the board's 5V supply input. The 1.25V reference voltage, common to the FPGA and DDR
SDRAM, is generated using a resistor voltage divider from the 2.5V rail.
LTC3412
All DDR SDRAM interface signals are terminated.
MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide
UG257 (v1.1) December 5, 2007
5.0V
2.5V
1.25V
Spartan-3E FPGA
See Table
See Table
See Table
VREF
VCCO_3
(B9) GCLK9
SD_CK_FB
Figure 13-1: FPGA Interface to Micron 512 Mbit DDR SDRAM
SD_A<12:0>
SD_DQ<15:0>
SD_BA<1:0>
SD_RAS
(C1)
SD_CAS
(C2)
SD_WE
(D1)
SD_UDM
(J1)
SD_LDM
(J2)
SD_UDQS
(G3)
SD_LDQS
(L6)
SD_CS
(K4)
SD_CKE
(K3)
SD_CK_N
(J4)
SD_CK_P
(J5)
Chapter 13
Figure 13-1. All
Micron 512 Mb DDR SDRAM
A[12:0]
DQ[15:0] VREF
BA[1:0] VDD
RAS# VDDQ
CAS#
WE#
UQM
MT46V32M16
(32Mx16)
LQM
UDQS
LDQS
CS#
CKE
CK#
CK
UG257_13_01_060806
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