Xilinx SelectIO 7 Series User Manual page 4

Date Version
05/13/2014 1.4
(Cont'd)
05/15/2015 1.5
09/18/2015 1.6
09/15/2016 1.7
09/27/2016 1.8
08/22/2017 1.9
05/08/2018 1.10
7 Series FPGAs SelectIO Resources User Guide
Added to list of criteria after
after Table 1-51. Updated V
Updated DLYIN connection in
description of PIPE_SEL in
first paragraph of Stability after an Increment/Decrement Operation, page
Removed center I/Os from
ODELAY Modes, replaced ODELAYCTRL with IDELAYCTRL.
In Table 3-1, added CLKDIVP and updated descriptions of OCLK and OCLKB. Updated
High-Speed Clock for Strobe-Based Memory Interfaces and Oversampling Mode -
OCLK and Reset Input - RST. Added IOBDELAY to
MEMORY Interface Type. Updated bullets in
Figure 3-7. Added sentence about ISERDESE2 being reset to
Bitslip Submodule. Removed Bitslip submodule from description of CLKDIV in
Table 3-6. Added TBYTE_CTL and TBYTE_SRC to
TQ, and OBUFT.O by one CLK edge.
Added paragraph about overvoltage protection mode to
During and After Configuration. Updated
In IOSTANDARD Attribute, replaced DIFF_HSTL18_II with DIFF_HSTL_II_18.
Reversed R and R
VRN VRP
Figure 1-50, Figure 1-52, Figure
Figure 1-62. Added note 2 to
Mitigate SSO Sensitivity.
Updated description of clock input C in
with S/R in Figure 2-17, Figure
Replaced SR with S/R throughout. Added note about set and reset pins to
Table 2-10. In RDY - Ready, updated sentence about RDY signal being deasserted if
REFCLK is held High or Low for more than one clock period.
In Table 3-6, changed TBYTEOUT port type from input to output.
Updated first paragraph of
Properties Reference Guide in
(IN_TERM) and 7 Series FPGA SelectIO
termination for unused I/Os to
OBUFT, and IOBUF.
Updated third bullet in OSERDESE2 Clocking
14:1 latency to 5 CLK cycles.
Added Spartan-7 family to Preface. Updated
describing CLK driven by BUFG and CLKDIV driven by a different BUFG from
NETWORKING Interface Type
Replaced HR with HP in second paragraph of
in ILOGIC Resources. Updated REFCLK_FREQUENCY value and description in
Table 2-5 and Table 2-14. Updated description of
CLKIN.
Updated descriptions of SHIFTOUT1, SHIFTOUT2, SHIFTIN1, and SHIFTIN2 in
Table 3-6. Updated input span to D1–D8 in
Serialization.
Expanded descriptions in
Attribute. Added note after
www.xilinx.com
Revision
Table 1-44. Added note to
Input column in Table
CCO
Figure 2-4. Updated Clock Input - C, page
Table 2-5 and Table 2-14. Added VAR_LOAD description to
Figure 2-16. Updated Data Output - DATAOUT, page
OVERSAMPLE Interface
Table
Special DCI Requirements for Some
resistors in left side IOB of DCI terminations in
1-54, Figure 1-57, Figure
Table 1-55. Added Vivado Design Suite to
IDELAY Ports
2-20, and Table 2-10.
V . Added reference to UG912: Vivado Design Suite
CCO
Uncalibrated Split Termination in High-Range I/O Banks
Attributes/Constraints. Added description of
PULLUP/PULLDOWN/KEEPER Attribute for IBUF,
Methods. In
Reset Input -
and OSERDESE2 Clocking
V . Expanded description of ZHOLD
CCO
Clock Input from Clock Buffer -
Timing Characteristics of 8:1 DDR
Parallel 3-state Inputs - T1 to T4
Table 3-11.
Table 1-48. Updated description
1-55. Added note 3 to Table
117. Updated
123.
Table 3-2. Updated bullets in
Type. Updated
Guidelines for Using the
3-7. In Figure 3-18, shifted OQ,
V . Added State of I/Os
CCO
Figure
1-58, Figure 1-60, and
Pin Planning to
and ODELAY Ports. Replaced SR
Table 2-1
Table 3-11, updated DDR
RST. Removed bullet
Methods.
and DATA_RATE_TQ
UG471 (v1.10) May 8, 2018
1-56.
135. In
Banks.
1-49,
and