Oserdese2 Timing Model And Parameters - Xilinx SelectIO 7 Series User Manual

Table 3-11: OSERDESE2 Latencies
Note:
edges of both clocks are phase aligned, the latency can vary by one cycle.

OSERDESE2 Timing Model and Parameters

This section discusses all timing models associated with the OSERDESE2 primitive.
Table 3-12
characteristics in the 7 series FPGA data sheets.
Table 3-12: OSERDESE2 Switching Characteristics
Setup/Hold
T
T
T
T
T
Sequential Delays
T
T
Combinatorial
T
T
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
DATA_RATE
SDR
DDR
In Table 3-11, the CLK and CLKDIV clock edges are normally not phase aligned. When the
describes the function and control signals of the OSERDESE2 switching
Symbol
/T
OSDCK_D OSCKD_D
/T
OSDCK_T OSCKD_T
/T
OSDCK_T OSCKD_T
/T
OSCCK_OCE OSCKC_OCE
/T
OSCCK_TCE OSCKC_TCE
OSCKO_OQ
OSCKO_TQ
OSCO_OQ
OSCO_TQ
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Output Parallel-to-Serial Logic Resources (OSERDESE2)
DATA_WIDTH
2:1
3:1
4:1
5:1
6:1
7:1
8:1
4:1
6:1
8:1
10:1
14:1
Description
D input Setup/Hold with respect to CLKDIV
T input Setup/Hold with respect to CLK
T input Setup/Hold with respect to CLKDIV
OCE input Setup/Hold with respect to CLK
TCE input Setup/Hold with respect to CLK
Clock to Out from CLK to OQ
Clock to Out from CLK to TQ
Asynchronous Reset to OQ
Asynchronous Reset to TQ
Latency
1 CLK cycle
2 CLK cycles
3 CLK cycles
4 CLK cycles
5 CLK cycles
6 CLK cycles
7 CLK cycles
2 CLK cycles
3 CLK cycles
4 CLK cycles
5 CLK cycles
5 CLK cycles
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