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IBUFDS_DIFF_OUT and IBUFGDS_DIFF_OUT
Figure 1-19
(O and OB). IBUFDS_DIFF_OUT and IBUFGDS_DIFF_OUT primitives are the same,
IBUFGDS_DIFF_OUT is used for clock inputs. These primitives are only recommended for
use by experienced Xilinx designers.
X-Ref Target - Figure 1-19
IBUFDS_DIFF_OUT_IBUFDISABLE
The IBUFDS_DIFF_OUT_IBUFDISABLE primitive shown in
input buffer with complementary differential outputs and a disable port that can be used
as an additional power saving feature for periods when the input is not used.
X-Ref Target - Figure 1-20
The IBUFDS_DIFF_OUT_IBUFDISABLE primitive can disable the input buffer and force
both the O and OB outputs to the fabric high when the USE_IBUFDISABLE attribute is set
to TRUE and the IBUFDISABLE signal is asserted High. If USE_IBUFDISABLE is set to
FALSE, this input is ignored and should be tied to ground. This feature can be used to
reduce power whenever the I/O is idle.
IBUFDS_IBUFDISABLE
The IBUFDS_IBUFDISABLE primitive shown in
with a disable port that can be used as an additional power saving feature for periods
when the input is not used.
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
shows the differential input buffer primitives with complementary outputs
IBUFDS_DIFF_OUT/IBUFGDS_DIFF_OUT
Input from
Device Pad
Figure 1-19: Differential Input Buffer Primitives With Complementary Outputs
(IBUFDS_DIFF_OUT/IBUFGDS_DIFF_OUT)
IBUFDS_DIFF_OUT_IBUFDISABLE
IBUFDISABLE
Figure 1-20: Differential Input Buffer With Complementary Outputs and Input
Buffer Disable (IBUFDS_DIFF_OUT_IBUFDISABLE)
www.xilinx.com
7 Series FPGA SelectIO Primitives
I
+
O
–
IB
OB
I
IB
Figure 1-21
Output to
FPGA
ug471_c1_25_041112
Figure 1-20
is a differential
O
OB
UG471_c1_67_041412
is a differential input buffer
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