Xilinx SelectIO 7 Series User Manual page 99

Table 1-55: V and V
CCO
I/O Standard
DIFF_SSTL18_II_DCI
DIFF_SSTL18_II_T_DCI
HSLVDCI_15
HSLVDCI_18
HSTL_I
HSTL_I_12
HSTL_I_18
HSTL_I_DCI
HSTL_I_DCI_18
HSTL_II
HSTL_II_18
HSTL_II_DCI
HSTL_II_DCI_18
HSTL_II_T_DCI
HSTL_II_T_DCI_18
HSUL_12
HSUL_12_DCI
LVCMOS12
LVCMOS15
LVCMOS18
LVCMOS25
LVCMOS33
LVDCI_15
LVDCI_18
LVDCI_DV2_15
LVDCI_DV2_18
LVDS
LVDS_25
SSTL12
SSTL12_DCI
SSTL12_T_DCI
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Requirements for Each Supported I/O Standard (Cont'd)
REF
I/O Bank
Availability
Output
HP 1.8
HP 1.8
HP 1.5
HP 1.8
Both 1.5
HP 1.2
Both 1.8
HP 1.5
HP 1.8
Both 1.5
Both 1.8
HP 1.5
HP 1.8
HP 1.5
HP 1.8
Both 1.2
HP 1.2
Both 1.2
Both 1.5
Both 1.8
HR 2.5
HR 3.3
HP 1.5
HP 1.8
HP 1.5
HP 1.8
HP 1.8
(2)
HR 2.5
HP 1.2
HP 1.2
HP 1.2
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Rules for Combining I/O Standards in the Same Bank
V (V)
CCO
Input with
Input
DIFF_TERM = TRUE
1.8 N/A
1.8 N/A
Any N/A
Any N/A
Any N/A
Any N/A
Any N/A
1.5 N/A
1.8 N/A
Any N/A
Any N/A
1.5 N/A
1.8 N/A
1.5 N/A
1.8 N/A
Any N/A
1.2 N/A
1.2 N/A
1.5 N/A
1.8 N/A
2.5 N/A
3.3 N/A
1.5 N/A
1.8 N/A
1.5 N/A
1.8 N/A
(1)
1.8 1.8
(1)
2.5 2.5
Any N/A
1.2 N/A
1.2 N/A
V (V)
REF
Input
N/A
N/A
0.75
0.9
0.75
0.6
0.9
0.75
0.9
0.75
0.9
0.75
0.9
0.75
0.9
0.6
0.6
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.6
0.6
0.6
99
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