Guidelines For Expanding The Parallel-To-Serial Converter Bit Width; Output Feedback; Oserdese2 Latencies; Default Interface Type Latencies - Xilinx SelectIO 7 Series User Manual

Chapter 3: Advanced SelectIO Logic Resources
Table 3-9
Table 3-9: OSERDESE2 SDR/DDR Data Width Availability
SDR Data Widths
DDR Data Widths

Guidelines for Expanding the Parallel-to-Serial Converter Bit Width

1.
2.
3.
4.
5.
6.
The slave inputs used for data widths requiring width expansion are listed in
Table 3-10: Slave Inputs Used for Data Width Expansion

Output Feedback

The OSERDESE2 pin OFB has two functions:
•
•

OSERDESE2 Latencies

DEFAULT Interface Type Latencies

The input to output latencies of OSERDESE2 blocks depend on the DATA_RATE and
DATA_WIDTH attributes. Latency is defined as a period of time between the following
two events: (a) when the rising edge of CLKDIV clocks the data at inputs D1–D8 into the
OSERDESE2, and (b) when the first bit of the serial stream appears at OQ.
summarizes the various OSERDESE2 latency values.
168
Send Feedback
lists the data width availability for SDR and DDR mode.
Both the OSERDESE2 modules must be adjacent master and slave pairs.
Set the SERDES_MODE attribute for the master OSERDESE2 to MASTER and the
slave OSERDESE2 to SLAVE. See
The user must connect the SHIFTIN ports of the MASTER to the SHIFTOUT ports of
the SLAVE.
The SLAVE only uses the ports D3 to D8 as an input.
DATA_WIDTH for Master and Slave are equal. See
The attribute INTERFACE_TYPE is set to DEFAULT.
Data Width
10
14
As a feedback path to the ISERDESE2 OFB pin. See
OSERDESE2.
As a connection to the ODELAYE2. The output of the OSERDESE2 can be routed
though the OFB pin and then delayed through the ODELAYE2.
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2, 3, 4, 5, 6, 7, 8
4, 6, 8, 10, 14
SERDES_MODE Attribute.
DATA_WIDTH
Slave Inputs Used
D3–D4
D3–D8
ISERDESE2 Feedback from
7 Series FPGAs SelectIO Resources User Guide
Attribute.
Table 3-10.
Table 3-11
UG471 (v1.10) May 8, 2018