Mobile_Ddr (Low Power Ddr); Summary Of Memory Interface Iostandards And Attributes Supported - Xilinx SelectIO 7 Series User Manual

Chapter 1: SelectIO Resources
Figure 1-69
differential HSUL_12 with bidirectional DCI signalling.
X-Ref Target - Figure 1-69
DCI
DIFF_HSUL_12_DCI
R 0 = 50
DIFF_HSUL_12_DCI
Ω
R 0 = 50
DIFF_HSUL_12_DCI
Figure 1-69: Differential HSUL_12 with DCI Bidirectional Signalling

MOBILE_DDR (Low Power DDR)

Table 1-39: Available I/O Bank Type
The MOBILE_DDR standard is for LPDDR and Mobile DDR memory buses.
MOBILE_DDR is defined by the JEDEC I/O standard JESD209A. It is a 1.8V single-ended
I/O standard that eliminates the need for V
support this standard for single-ended signaling and differential outputs. The differential
outputs drive the CK/CK# pins.
The differential (DIFF_) version uses complementary single-ended drivers for outputs,
and differential receivers for inputs.

Summary of Memory Interface IOSTANDARDs and Attributes Supported

Table 1-40
MOBILE_DDR I/O standards and attributes supported.
Table 1-41
MOBILE_DDR I/O standards and attributes supported.
Table 1-42
HSTL, SSTL, HSUL, and MOBILE_DDR I/O standards.
88
Send Feedback
shows a sample circuit illustrating a board topology (with no termination) for
IOB
Ω
+
–
HR
Available N/A
lists the available 7 series FPGA single-ended HSTL, SSTL, HSUL, and
lists the available 7 series FPGA differential HSTL, SSTL, HSUL, and
lists the SLEW attribute for the 7 series FPGA single-ended and differential
www.xilinx.com
IOB
DIFF_HSUL_12_DCI
Z 0
DIFF_HSUL_12_DCI
Z 0
DIFF_HSUL_12_DCI
HP
and V
REF
7 Series FPGAs SelectIO Resources User Guide
Ω
R 0 = 50
Ω
R 0 = 50
+
–
ug471_c1_59_011811
voltage supplies. 7 series FPGAs
TT
UG471 (v1.10) May 8, 2018