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Chapter 3:
Advanced SelectIO Logic Resources
names do not change when a different bus input width, including when two ISERDESE2
are cascaded together to form 10 or 14 bits. In DDR mode, the data input (D) switches at
every CLK edge (rising and falling).
X-Ref Target - Figure 3-10
Clock Event 1
•
Clock Event 2
•
ISERDESE2 VHDL and Verilog Instantiation Template
VHDL and Verilog instantiation templates are available in the Libraries Guide for all
primitives and submodules.
In VHDL, each template has a component declaration section and an architecture section.
Each part of the template should be inserted within the VHDL design file. The port map of
the architecture section should include the design signal names.
BITSLIP Submodule
All ISERDESE2 blocks in 7 series devices contain a Bitslip submodule. This submodule is
used for word-alignment purposes in source-synchronous networking-type applications.
Bitslip reorders the parallel data in the ISERDESE2 block, allowing every combination of a
repeating serial pattern received by the deserializer to be presented to the FPGA fabric.
This repeating serial pattern is typically called a training pattern (training patterns are
supported by many networking and telecommunications standards). In some interfaces,
this can be a slow forwarded clock, which can be considered to be a repeating bit pattern.
Bitslip Operation
By asserting the Bitslip pin of the ISERDESE2 block, the incoming serial data stream is
reordered at the parallel side. This operation is repeated until the required training pattern
is seen at the ISERDESE2 outputs. The tables in
operation in SDR and DDR mode. (Bit 8 of an input ISERDESE2 is the first bit received.) For
illustrative purposes the data width is eight. The Bitslip operation is synchronous to
CLKDIV. In SDR mode, every Bitslip operation causes the output pattern to shift left by
one. In DDR mode, every Bitslip operation causes the output pattern to alternate between
158
Send Feedback
1
2
CLK
T
ISCCK_CE
CE
D
Figure 3-10: ISERDESE2 Input Data Timing Diagram
At time T
, before Clock Event 1, the clock enable signal becomes valid-High
ISCCK_CE
and the ISERDESE2 can sample data.
At time T
, before Clock Event 2, the input data pin (D) becomes valid and is
ISDCK_D
sampled at the next positive clock edge.
www.xilinx.com
T
ISDCK_D
Figure 3-11
illustrate the effects of a Bitslip
7 Series FPGAs SelectIO Resources User Guide
ug471_c3_10_012211
UG471 (v1.10) May 8, 2018
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