Xilinx SelectIO 7 Series User Manual page 108

Chapter 2: SelectIO Logic Resources
X-Ref Target - Figure 2-4
ILOGIC can support the following operations:
•
•
•
•
The ILOGIC block registers have a common clock enable signal (CE1) that is active High by
default. If left unconnected, the clock enable pin for any storage element defaults to the
active state.
108
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D
DDLY
DLYFABRIC
ZHOLD_DELAY
DLVIFF DLYIN
OFB
TFB
CE1
CLK
CLKB
S/R
Figure 2-4: ILOGICE3 Block Diagram
Edge-triggered D-type flip-flop
IDDR mode (OPPOSITE_EDGE or SAME_EDGE or SAME_EDGE_PIPELINED). See
Input DDR Overview (IDDR), page 109
Level sensitive latch
Asynchronous/combinatorial
www.xilinx.com
D
Latch
CE
FF
CK
DDR
CKB
S/R
for further discussion on input DDR.
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
O
Q1 Q1
Q2
Q2
UG471_c2_02_081215