Xilinx SelectIO 7 Series User Manual page 30

Chapter 1: SelectIO Resources
To correctly use DCI in 7 series devices:
1.
2.
3.
Table 1-6: I/O Standards with DCI Inputs that Do Not Require Reference Resistors
LVDCI_18
LVDCI_15
4.
5.
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V pins must be connected to the appropriate V
CCO
IOSTANDARDs in that I/O bank.
Correct DCI I/O buffers must be used in the software either by using IOSTANDARD
attributes or instantiations in the HDL code.
DCI standards require connecting external reference resistors to the multipurpose pins
(VRN and VRP). When this is required, these two multipurpose pins cannot be used as
general-purpose I/O in the I/O bank using DCI or in the master I/O bank when
cascading DCI. Refer to the 7 series FPGA pinout tables for the specific pin locations.
Pin VRN must be pulled up to V
down to ground by its reference resistor. An exception to this requirement comes when
cascading DCI in slave I/O banks since the VRN and VRP pins can be used as
general-purpose I/O.
DCI standards with the controlled impedance driver can be used on input-only
signals. For this case, if these pins are the only pins using DCI standards in a given
I/O bank, that bank does not require connecting the external reference resistors to the
VRP/VRN pins. When these DCI-based I/O standards are the only ones in a bank, the
VRP and VRN pins in that bank can be used as general-purpose I/O.
• DCI inputs that do not require reference resistors on VRP/VRN are shown in
Table 1-6.
LVDCI_DV2_18
LVDCI_DV2_15
The value of the external reference resistors should be selected to give the desired
output driver impedance or split-termination impedance. For example, when using
LVDCI_15, to achieve a 50Ω output driver impedance, the external reference resistors
used on the VRN and VRP pins should each be 50Ω. When using SSTL15_T_DCI, to
achieve a 50Ω Thevenin equivalent termination (R) to V
resistors should each be 100Ω, which is (2R). Xilinx requires that the exact same value
of the resistance be used on the VRP and VRN pins in order to achieve the expected
DCI behavior.
Follow the DCI I/O banking rules:
a. V must be compatible for all of the inputs in the same I/O bank or in a group of
REF
I/O banks when using DCI cascade.
b. V must be compatible for all of the inputs and outputs in the same I/O bank.
CCO
c. Split termination, controlled impedance driver, and controlled impedance driver
with half impedance can co-exist in the same bank.
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voltage based on the
CCO
by its reference resistor. Pin VRP must be pulled
CCO
HSLVDCI_18
HSLVDCI_15
7 Series FPGAs SelectIO Resources User Guide
HSUL_12_DCI
DIFF_HSUL_12_DCI
/2, the external reference
CCO
UG471 (v1.10) May 8, 2018