Sstl135_Dci; Sstl18_Ii_T_Dci, Sstl15_T_Dci, Sstl135_T_Dci, Diff_Sstl18_Ii_T_Dci; Diff_Sstl15_T_Dci, Diff_ Sstl135_T_Dci; Sstl12, Sstl12_Dci, Sstl12_T_Dci, Diff_Sstl12, Diff_Sstl12_Dci, Diff_Sstl12_T_Dci - Xilinx SelectIO 7 Series User Manual

Note:
applications. Refer to UG586: Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions v2.0
User Guide for details.
SSTL18_II_DCI, SSTL_15_DCI, SSTL135_DCI, DIFF_SSTL18_II_DCI,
DIFF_SSTL_15_DCI, DIFF_ SSTL135_DCI
Table 1-34: Available I/O Bank Type
The DCI standards provide tuned internal parallel split-termination resistors that are
always present (for receivers). The value of both the pull-up and pull-down resistors
mirror the resistance measured on the VRN/VRP pins, creating the Thevenin equivalent
resistance to the V
complementary single-ended drivers for outputs and differential receivers for inputs.
SSTL18_II_T_DCI, SSTL15_T_DCI, SSTL135_T_DCI,
DIFF_SSTL18_II_T_DCI, DIFF_SSTL15_T_DCI, DIFF_ SSTL135_T_DCI
Table 1-35: Available I/O Bank Type
These standards are only available for bidirectional (input and output) signals. The T_DCI
standards provide tuned internal parallel split-termination resistors that are only present
when the 3-state control is enabled on the output buffer. The termination is disabled
whenever the output buffer is driving. The value of both the pull-up and pull-down
resistors mirror the resistance measured on the VRN/VRP pins, creating the Thevenin
equivalent resistance to the V
complementary single-ended drivers for outputs and differential receivers for inputs.
SSTL12, SSTL12_DCI, SSTL12_T_DCI, DIFF_SSTL12,
DIFF_SSTL12_DCI, DIFF_SSTL12_T_DCI
Table 1-36: Available I/O Bank Type
DCI provides tuned internal parallel split-termination resistors that are always present for
receivers. DCI versions are only available for unidirectional (input or output) signals. The
T_DCI versions limit the resistors to only be present when the 3-state control is enabled on
the output buffer (only when receiving). With T_DCI, the termination is disabled
whenever the output buffer is driving. The T_DCI versions are only available for
bidirectional signals (input and output). The value of both the pull-up and pull-down
resistors mirror the resistance measured on the VRN/VRP pins, creating the Thevenin
equivalent resistance to the V
complementary single-ended drivers for outputs, and differential receivers for inputs.
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
A lower resistance value can be used for the parallel end-termination resistors in some DDR3
HR HP
N/A Available
/2 mid-point level. The differential (DIFF_) versions use
CCO
HR HP
N/A Available
CCO
HR HP
N/A Available
CCO
www.xilinx.com
Supported I/O Standards and Terminations
/2 mid-point level. The differential (DIFF_) versions use
/2 mid-point level. The differential (DIFF_) versions use
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