Serial Input Data From Idelaye2 - Ddly; Serial Input Data From Oserdese2 - Ofb; High-Speed Clock For Strobe-Based Memory Interfaces And Oversampling Mode - Oclk; Reset Input - Rst - Xilinx SelectIO 7 Series User Manual

Serial Input Data from IDELAYE2 - DDLY

The serial input data port (DDLY) is the serial (high-speed) data input port of the
ISERDESE2. This port works in conjunction only with the 7 series FPGA IDELAYE2
resource. See

Serial Input Data from OSERDESE2 - OFB

The serial input data port (OFB) is the serial (high-speed) data input port of the
ISERDESE2. This port works in conjunction only with the 7 series FPGA OSERDESE2 port
OFB. See
High-Speed Clock for Strobe-Based Memory Interfaces and
Oversampling Mode - OCLK
The OCLK clock input synchronizes data transfer in strobe-based memory interfaces. The
OCLK clock is only unused when INTERFACE_TYPE is set to NETWORKING.
The OCLK clock input can be used to transfer strobe-based memory data onto a
free-running clock domain. OCLK is a free-running FPGA clock at the same frequency as
the strobe on the CLK input. The domain transfer from CLK to OCLK is shown in the
Figure 3-5
the delay of the strobe signal to the CLK input (e.g., using IDELAY). Examples of setting
the timing of this domain transfer for MEMORY_DDR3 and MEMORY_QDR modes are
given in the Memory Interface Generator (MIG). When INTERFACE_TYPE is
NETWORKING, this port is unused.

Reset Input - RST

When asserted, the reset input causes the outputs of most data flip-flops in the CLK and
CLKDIV domains to be driven Low asynchronously. The exceptions are the first four
flip-flops in the input structure whose value after RESET is selectable via attributes on the
component. When deasserted synchronously with CLKDIV, internal logic re-times this
deassertion to the first rising edge of CLK. Every ISERDESE2 in a multiple bit input
structure should therefore be driven by the same reset signal, asserted, and deasserted
synchronously to CLKDIV to ensure that all ISERDESE2 elements come out of reset in
synchronization. The reset signal should only be deasserted when it is known that CLK
and CLKDIV are stable and present, and should be a minimum of two CLKDIV pulses
wide. After deassertion of reset, the output is not valid until after two CLKDIV cycles.
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Input Serial-to-Parallel Logic Resources (ISERDESE2)
Using D and DDLY in the
ISERDESE2 Feedback from OSERDESE2
block diagram. The timing of the domain transfer is set by the user by adjusting
www.xilinx.com
ISERDESE2.
.
Send Feedback
149