Xilinx SelectIO 7 Series User Manual page 73

Figure 1-56
HSTL class-II (1.5V or 1.8V) with on-chip split-thevenin termination. In a specific circuit,
all drivers and receivers must be at the same voltage level (either 1.5V or 1.8V); they are not
interchangeable. Only HP I/O banks support the T_DCI standards. The internal
split-termination resistors are only present when the output buffers are 3-stated.
X-Ref Target - Figure 1-56
DCI
Not 3-stated (T pin logic Low)
DIFF_HSTL_II_DCI_T
DIFF_HSTL_II_DCI_T_18
0
DIFF_HSTL_II_DCI_T
DIFF_HSTL_II_DCI_T_18
0
DIFF_HSTL_II_DCI_T
DIFF_HSTL_II_DCI_T_18
+
–
Figure 1-56: Differential HSTL Class II (1.5V or 1.8V) DCI with Split-Thevenin Termination (3-state)
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
shows a sample circuit illustrating a termination technique for differential
3-stated (T pin logic High)
IOB
IOB
V
CCO
for DIFF_HSTL_II_DCI_T
V
CCO
for DIFF_HSTL_II_DCI_T_18
Z 0
Z 0
V
DIFF_HSTL_II_DCI_T
V
DIFF_HSTL_II_DCI_T_18
www.xilinx.com
Supported I/O Standards and Terminations
= 1.5V
= 1.8V
DIFF_HSTL_II_DCI_T
DIFF_HSTL_II_DCI_T_18
R = 2Z 0 = 100Ω
VRN
R = 2Z 0 = 100Ω
VRP
DIFF_HSTL_II_DCI
DIFF_HSTL_II_DCI_T_18
= 1.5V for
CCO
= 1.8V for
CCO DIFF_HSTL_II_DCI
DIFF_HSTL_II_DCI_T_18
R = 2Z 0 = 100Ω
VRN
R = 2Z 0 = 100Ω
VRP
1
1
+
–
ug471_c1_46_021214
73
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