Xilinx SelectIO 7 Series User Manual page 24

Chapter 1: SelectIO Resources
The guidelines when using DCI cascading are as follows:
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DCI cascading is only available through a column of HP I/O banks
The master and slave SelectIO banks must all reside on the same HP I/O column on
the device and can span the entire column unless there is an interposer boundary.
DCI cascading cannot pass through the interposer boundaries of the larger
Virtex-7 devices with stacked silicon interconnect (SSI) technology. This includes the
XC7V2000T and XC7VX1140T devices. For these devices, the I/O banks that are
separated by these interposer boundaries are shown in the figures of the "Die Level
Bank Numbering Overview" section of UG475: 7 Series FPGAs Packaging and Pinout
Specifications.
Master and slave I/O banks must have the same V
voltage.
I/O banks in the same HP I/O column that are not using DCI (pass-through banks)
do not have to comply with the V
settings.
DCI I/O banking compatibility rules must be satisfied across all master and slave
banks (for example, only one DCI I/O standard using single termination type is
allowed across all master and slave banks).
To locate I/O banks that reside in the same I/O column, refer to the figures of the "Die
Level Bank Numbering Overview" section of UG475: 7 Series FPGAs Packaging and
Pinout Specifications.
For specific information on implementing DC cascading in a design, see
DCI_CASCADE Constraint, page
Xilinx recommends that unused banks be powered up because leaving the V
of unused I/O banks floating reduces the level of ESD protection on these pins and
the I/O pins in the bank. If the bank is unpowered, DCI can still be cascaded through
the unpowered bank.
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and V
CCO
and V voltage rules for combining DCI
CCO REF
46.
7 Series FPGAs SelectIO Resources User Guide
(if applicable)
REF
pins
CCO
UG471 (v1.10) May 8, 2018