Iserdese2 Attributes - Xilinx SelectIO 7 Series User Manual

Chapter 3: Advanced SelectIO Logic Resources

ISERDESE2 Attributes

Table 3-2
each attribute follows the table. For more information on applying these attributes in UCF,
VHDL, or Verilog code, refer to the Xilinx ISE Software Manual.
Table 3-2: ISERDESE2 Attributes
Attribute Name
DATA_RATE
DATA_WIDTH
DYN_CLKDIV_INV_EN Enables DYNCLKDIVSEL inversion when
DYN_CLK_INV_EN
INTERFACE_TYPE
NUM_CE
OFB_USED
SERDES_MODE
INIT_Q1
INIT_Q2
INIT_Q3
INIT_Q4
SRVAL_Q1
150
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summarizes all the applicable ISERDESE2 attributes. A detailed description of
Description
Enables incoming data stream to be
processed as SDR or DDR data. See
DATA_RATE Attribute.
Defines the width of the serial-to-parallel
converter. The legal value depends on the
DATA_RATE attribute (SDR or DDR). See
DATA_WIDTH Attribute.
TRUE and disables HDL inversions on
CLKDIV pin. See Dynamic Clock
Enables DYNCLKSEL inversion when TRUE
and disables HDL inversions on CLK and
CLKB pins. See Dynamic Clock
Chooses the ISERDESE2 use model. See
INTERFACE_TYPE Attribute.
Defines the number of clock enables. See
NUM_CE Attribute.
Enables the path from the OLOGICE2/3,
OSERDESE2 OFB pin to the ISERDESE2 OFB
pin. Disables the use of the D input pin.
Defines whether the ISERDESE2 module is a
master or slave when using width expansion.
See SERDES_MODE Attribute.
Sets the initial value for the first sample
register.
Sets the initial value for the second sample
register.
Sets the initial value for the third sample
register.
Sets the initial value for the fourth sample
register.
Sets the value after reset of the first sample
register.
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String: SDR or DDR
Integer: 2, 3, 4, 5, 6, 7, 8, 10 or 14.
If DATA_RATE = DDR, value is
limited to 4, 6, 8, 10, or 14.
If DATA_RATE = SDR, value is
limited to 2, 3, 4, 5, 6, 7, or 8.
Boolean: TRUE or FALSE
Inversions.
Boolean: TRUE or FALSE
Inversions.
String: MEMORY,
MEMORY_DDR3,
MEMORY_QDR,
OVERSAMPLE, or
NETWORKING
Integer: 1 or 2
Boolean: TRUE or FALSE
String: MASTER or SLAVE
Binary: 0 or 1
Binary: 0 or 1
Binary: 0 or 1
Binary: 0 or 1
Binary: 0 or 1
7 Series FPGAs SelectIO Resources User Guide
Default
Value
Value
DDR
4
FALSE
FALSE
MEMORY
2
FALSE
MASTER
0
0
0
0
1
UG471 (v1.10) May 8, 2018